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型號(hào)：	μPD98501
廠商：	NEC Corp.
英文描述：	Network Controller(網(wǎng)絡(luò)控制器)
中文描述：	網(wǎng)絡(luò)控制器（網(wǎng)絡(luò)控制器）
文件頁(yè)數(shù)：	98/671頁(yè)
文件大?。?/td>	2229K
代理商：	ΜPD98501

Preliminary User’s Manual S14767EJ1V0UM00

2.3.7.3 Delay slots

MIPS16 instructions normally execute in one cycle. However, some instructions have special requirements that

must be met to assure optimum instruction flow. The instructions include all Load, Branch, and Multiply/Divide

instructions.

(1) Load delay slots

MIPS16 operates with delayed loads. This is similar to the method used by 32-bit MIPS instruction sets. If

another instruction references the load destination register before the load operation is completed, one cycle

occurs automatically. To assure the best performance, the compiler should always schedule load delay slots as

early as possible.

(2) Branch delay slots not supported

Unlike for 32-bit MIPS instructions, there are no branch delay slots for branch instructions in MIPS16. If a branch

is taken, the instruction that immediately follows the branch (instruction corresponding to 32-bit MIPS delay slot) is

cancelled. There are no restrictions on the instruction that follows a branch instruction, and such instruction is

executed only when a branch is not taken. Branches, jumps, and extended instructions are permitted in the

instruction slot after a branch.

(3) Jump delay slots

With MIPS16, there is a delay of one cycle after each jump instruction. The processor executes any instruction in

the jump delay slot before it executes the jump target instruction. Two restrictions apply to any instruction placed

in the jump delay slot:

Do not specify a branch or jump in the delay slot.

Do not specify an extended instruction (32-bits) in the delay slot. Doing so will make the results

unpredictable.

(4) Multiply and divide scheduling

Multiply and divide latency depends on the hardware implementation. If an MFLO or MFHI instruction references

the Multiply or Divide result registers before the result is ready, the pipeline stalls until the operation is complete

and the result is available. However, to assure the best performance, the compiler should always schedule

Multiply and Divide instructions as early as possible.

MIPS16 requires that all MFHI and MFLO instructions be followed by two instructions that do not write to the HI or

LO registers. Otherwise, the data read by MFLO or MFHI will be undefined. The Extend instruction is counted

singly as one instruction.

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