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CHAPTER 2 V
R
4120A
Preliminary User’s Manual S14767EJ1V0UM00
137
Table 2-48. Comparison of useg and xuseg
Address Bit
Status Register Bit Value
Segment
Address Range
Size
Value
KSU
EXL
ERL
UX
Name
32-bit
A31 = 0
10
0
0
0
useg
0x0000 0000
to
0x7FFF FFFF
2 Gbytes
(2
31
bytes)
64-bit
A(63:40) = 0
10
0
0
1
xuseg
0x0000 0000 0000 0000
to
0x0000 00FF FFFF FFFF
1 Tbyte
(2
40
bytes)
(1) useg (32-bit mode)
In User mode, when UX = 0 in the Status register and the most significant bit of the virtual address is 0, this virtual
address space is labeled useg.
Any attempt to reference an address with the most-significant bit set while in User mode causes an Address Error
exception (see
Section 2.6 Exception Processing
).
The TLB Mismatch exception vector is used for TLB misses.
(2) xuseg (64-bit mode)
In User mode, when UX = 1 in the Status register and bits 63 to 40 of the virtual address are all 0, this virtual
address space is labeled xuseg.
Any attempt to reference an address with bits 63 to 40 equal to 1 causes an Address Error exception (see
Section
2.6 Exception Processing
).
The XTLB Mismatch exception vector is used for TLB misses.
2.5.2.6 Supervisor-mode virtual addressing
Supervisor mode shown in Figure 2-39 is designed for layered operating systems in which a true kernel runs in
Kernel mode, and the rest of the operating system runs in Supervisor mode.
The processor operates in Supervisor mode when the Status register contains the following bit-values:
—
KSU = 01
—
EXL = 0
—
ERL = 0
In conjunction with these bits, the SX bit in the Status register selects Supervisor mode addressing:
—
When SX = 0:
—
When SX = 1:
32-bit supervisor space is selected.
64-bit supervisor space is selected.
Figure 2-39 shows the supervisor mode address mapping, and Table 2-49 lists the characteristics of the
Supervisor mode segments.