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Preliminary User’s Manual S14767EJ1V0UM00
25
CHAPTER 1 INTRODUCTION
The
μ
PD98501 is a high performance controller which can perform the protocol conversion between IP Packets
and ATM Cells, which is especially suitable for ADSL modem and it includes high performance MIPS
based 64bit
RISC processor V
R
4120A CPU core, ATM Cell Processor, Ethernet Controller, USB controller Block, UTOPIA2
interface and SDRAM interface.
1.1 Features
Includes high performance MIPS based 64-bit RISC processor V
R
4120A
Can perform RTOS and network middleware (M/W) on the chip
Includes interface for PROM and flash ROM used for storing boot program
Includes 32bit RISC controller, as ATM Cell processor
Software SAR processing by RISC controller affords flexibility for specification update
Supports CBR/VBR/ABR/UBR/GFR(TBD) service classes
Includes 2-channel 10/100Mbps Ethernet controller compliant to IEEE802.3,IEEE 802.3u and IEEE802.3x
Can directly connect external Ethernet PHY device through 3.3V MII interface
Includes USB full speed function controller compliant to USB specification 1.1
Supports operation conforming to the USB Communication Device Class Specification
Can directly connect 16Mbit and 64Mbit SDRAM as external memory
Includes 8bit 33MHz UTOPIA level 2 interface compliant to ATM Forum af-phy-0039
Includes boundary scan function(JTAG) compliant to IEEE 1149.1
Includes serial N-Wire interface for field debug
Includes Micro Wire interface
Includes 2ch general purpose timers
Using advanced CMOS technology
Supply Voltage 2.5V (required 3.3V supply for 3.3V interface)
Package 352-pin T-BGA
1.2 Ordering Information
Part Number
Package
μ
PD98501N7-F6
352-pin Tape BGA (35
×
35)