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CHAPTER 2 V
R
4120A
60
Preliminary User’s Manual S14767EJ1V0UM00
(d) Special instructions are break and extend instructions. The break instruction transfers control to an exception
handler. The extend instruction extends the immediate field of the next instruction. They are RR- and I-types.
When extending the immediate field of the next instruction by using the extend instruction, one cycle is needed
for executing the extend instruction, and another cycle is needed for executing the next instruction.
For more details of each instruction’s operation, refer to
Section 2.3 MIPS16 Instruction Set
and
APPENDIX B
MIPS16 INSTRUCTION SET FORMAT
.
2.1.4 Data formats and addressing
The V
R
4120A uses following four data formats:
"
Doubleword (64 bits)
"
Word (32 bits)
"
Halfword (16 bits)
"
Byte (8 bits)
For the
μ
PD98501, byte ordering within all of the larger data formats - halfword, word, doubleword - can be
configured in either big-endian or little-endian order.
Endianness refers to the location of byte 0 within the multi-byte data structure.
When configured as a little-endian system, byte 0 is always the least-significant (rightmost) byte, which is
compatible with iAPX and DEC VAX conventions. Figures 2-5 and 2-6 show this configuration.
Figure 2-5. Little-Endian Byte Ordering in Word Data
12
12
13
14
15
0
15
16
8
23
24
7
31
8
8
9
10
11
4
4
5
6
7
0
0
1
2
3
Low-order
address
High-order
address
Word
address
Bit No.
Remarks 1.
The lowest byte is the lowest address.
2.
The address of word data is specified by the lowest byte’s address.
Figure 2-6. Little-Endian Byte Ordering in Double Word Data
16
23
0
31
32
8 7
63
8
0
Low-order
address
High-order
address
Double word
address
Half word
22
15
14
7
6
21
20
13
12
5
4
19
18
11
10
3
2
17
16
9
8
1
0
16 15
Word
Byte
48 47
Remarks 1.
The lowest byte is the lowest address.
2.
The address of word data is specified by the lowest byte’s address.