![](http://datasheet.mmic.net.cn/380000/-PD98501_datasheet_16745028/-PD98501_426.png)
CHAPTER 6 USB CONTROLLER
426
Preliminary User’s Manual S14767EJ1V0UM00
Bit30 is used to discriminate between the Buffer Descriptor and Link Pointer. When set to
1, this bit indicates the Buffer Descriptor.
The "Size" field indicates the buffer size. As the buffer size, a value between 1 and 64K
bytes can be set. The "Buffer Address" field indicates the head address of the buffer.
This is the link pointer. It indicates the last Buffer Directory.
Bit31 is usually set to 0.
Bit30 is used to discriminate between the Buffer Descriptor and Link Pointer. When set to
0, this bit indicates the Link Pointer.
The "Buffer Directory Address" field indicates the head address of the next Buffer
Directory.
Rx Link Pointer:
6.6.3 Receive pool settings
USB Controller uses two receive pools.
Pool0
For EndPoint0 (Control) and EndPoint6 (Interrupt)
Pool1
For EndPoint2 (Isochronous)
Pool2
For EndPoint4 (Bulk)
The data in each of these two pools is written into the corresponding registers.
Pool0
USB Rx Pool0 Information Register
USB Rx Pool0 Address Register
Pool1
USB Rx Pool1 Information Register
USB Rx Pool1 Address Register
Pool2
USB Rx Pool2 Information Register
USB Rx Pool2 Address Register
(Address: 50H)
(Address: 54H)
(Address: 58H)
(Address: 5CH)
(Address: 60H)
(Address: 64H)
The V
R
4120A RISC Processor can know the current status of each pool by reading these registers.
Upon initialization, after the V
R
4120A RISC Processor secures a receive pool area in the system memory area, it
makes the settings for the pool by setting the head address of the pool, plus the number of Buffer Directories that the
pool contains. The V
R
4120A RISC Processor can write values only into the Alert filed of four registers above. Other
filed must be set using USB Command Register and USB Command Address Register.
The V
R
4120A RISC Processor adds Buffer Directories to each pool by using the USB Command Register
(Address: 40H) and the USB Command Address Register (Address: 44H).
To add Buffer Directories to a receive pool, the V
R
4120A RISC Processor performs the following processing.
(1)
The V
R
4120A RISC Processor secures the Buffer Directory to be added to the pool, and the buffer, in
system memory. When multiple Buffer Directories are to be added, they are linked in advance.
(2)
The V
R
4120A RISC Processor writes the head address of the Buffer Directory to be added into the link
pointer to the last Buffer Directory in the list of dependent Buffer Directories in the pool.
(3)
The V
R
4120A RISC Processor writes the head address of the Buffer Directory to be added into the USB
Command Address Register (Address: 44H).
(4)
The V
R
4120A RISC Processor writes the pool number and size of the Buffer Directory to be added into
the USB Command Register (Address: 40H).