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CHAPTER 2 V
R
4120A
154
Preliminary User’s Manual S14767EJ1V0UM00
2.5.5.6 EntryHi register (10)
The EntryHi register is write-accessible. It is used to access the on-chip TLB. The EntryHi register holds the high-
order bits of a TLB entry for TLB read and write operations. If a TLB Mismatch, TLB Invalid, or TLB Modified
exception occurs, the EntryHi register holds the high-order bit of the TLB entry. The EntryHi register is also set with
the virtual page number (VPN2) for a virtual address where an exception occurred and the ASID. See
Section 2.6
Exception Processing
for details of the TLB exception.
The ASID is used to read from or write to the ASID field of the TLB entry. It is also checked with the ASID of the
TLB entry as the ASID of the virtual address during address translation.
The EntryHi register is accessed by the TLBP, TLBWR, TLBWI, and TLBR instructions.
Figure 2-50. EntryHi Register
39
40
(a) 32-bit mode
8
3
21
0
31
11
10
8
7
VPN2
0
ASID
(b) 64-bit mode
62
61
8
3
2
22
29
0
63
11
10
8
7
R
Fill
VPN2
0
ASID
VPN2: Virtual page number divided by two (mapping to two pages)
ASID : Address space ID. An 8-bit ASID field that lets multiple processes share the TLB; each process has a
distinct mapping of otherwise identical virtual page numbers.
R
: Space type (00
→
user, 01
→
supervisor, 11
→
kernel). Matches bits 63 and 62 of the virtual address.
Fill
: RFU. Ignored on write. When read, returns zero.
0
: RFU. Write 0 in a write operation. When this field is read, 0 is read.