CHAPTER 2 V
R
4120A
Preliminary User’s Manual S14767EJ1V0UM00
135
—
Shown at the bottom of Figure 2-37 is the virtual address space in which the page size is 256 Kbytes and the
offset is 18 bits. The 22 bits excluding the ASID field represents the VPN, enabling selecting a page table of
4 M entries.
Figure 2-37. 64-bit Mode Virtual Address Translation
31
PFN
32-bit physical address
10
24
30
8
0
0
9
10
39
40
61
62
63
64
71
ASID
Offset
TLB
18
24
22
8
0
17
18
39
40
61
62
63
64
71
ASID
TLB
0 or -1
0 or -1
VPN
Offset
VPN
Offset
Bits 62 and 63 of the virtual
address select the user,
supervisor, or kernel
address space.
Virtual address for 4 M (2
22
) 256-Kbyte pages
Virtual address for 1 G (2
30
) 1-Kbyte pages
30 bits = 1 G pages
The offset is passed to
physical address without
being changed.
The offset is passed to
physical address without
being changed.
Virtual-to-physical address
translation with the TLB
Virtual-to-physical address
translation with the TLB
22 bits = 4 M pages
2.5.2.4 Operating modes
The processor has three operating modes that function in both 32- and 64-bit operations:
—
User mode
—
Supervisor mode
—
Kernel mode
User and Kernel modes are common to all V
R
-Series processors. Generally, Kernel mode is used to execute the
operating system, while User mode is used to run application programs. The V
R
4000 series processors have a third
mode, which is called Supervisor mode and categorized in between User and Kernel modes. This mode is used to
configure a high-security system.
When an exception occurs, the CPU enters Kernel mode, and remains in this mode until an exception return
instruction (ERET) is executed. The ERET instruction brings back the processor to the mode in which it was just
before the exception occurs.