![](http://datasheet.mmic.net.cn/380000/-PD98501_datasheet_16745028/-PD98501_101.png)
CHAPTER 2 V
R
4120A
Preliminary User’s Manual S14767EJ1V0UM00
101
Table 2-35. Load and Store Instructions (3/3)
Instruction
Format and Description
SW ry, offset (rx)
The 5-bit immediate is shifted left two bits, zero extended, and then added to the contents of general
register rx to form the virtual address. The contents of general register ry are stored to the memory
location specified by the address.
If either of the two lower bits of the address is not 0, an address error exception is generated.
SW rx, offset (sp)
The 8-bit immediate is shifted left two bits, zero extended, and then added to the contents of general
register sp to form the virtual address. The contents of general register rx are stored to the memory
location specified by the address.
If either of the two lower bits of the address is not 0, and address error exception is generated.
Store Word
SW ra, offset (sp)
The 8-bit immediate is shifted left two bits, zero extended, and then added to the contents of general
register sp to form the virtual address. The contents of general register ra are stored to the memory
location specified by the address.
If either of the two lower bits of the address is not 0, an address error exception is generated.
SD ry, offset (rx)
The 5-bit immediate is shifted left three bits, zero extended to 64 bits, and then added to the contents
of general register rx to form the virtual address. The 64 bits of general register ry are stored to the
memory location specified by the address. If any of the lower three bits of the address is not 0, an
address error exception is generated.
This operation is defined in the 64-bit mode and the 32-bit kernel mode. When this instruction is
executed in the 32-bit user/supervisor mode, a reserved instruction exception is generated.
SD ry, offset (sp)
The 5-bit immediate is shifted left three bits, zero extended to 64 bits, and then added to the contents
of general register sp to form the virtual address. The 64 bits of general register ry are stored to the
memory location specified by the address.
If any of the lower three bits of the address is not 0, an address error exception is generated.
This operation is defined in the 64-bit mode and the 32-bit kernel mode. When this instruction is
executed in the 32-bit user/supervisor mode, a reserved instruction exception is generated.
Store Doubleword
SD ra, offset (sp).
The 8-bit immediate is shifted left three bits, zero extended to 64 bits, and then added to the contents
of general register sp to form the virtual address. The 64 bits of general register ra are stored to the
memory location specified by the memory.
If any of the three lower bits of the address is not 0, an address error exception is generated.
This operation is defined in the 64-bit mode and the 32-bit kernel mode. When this instruction is
executed in the 32-bit user/supervisor mode, a reserved instruction exception is generated.