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型號(hào)：	μPD98501
廠商：	NEC Corp.
英文描述：	Network Controller(網(wǎng)絡(luò)控制器)
中文描述：	網(wǎng)絡(luò)控制器（網(wǎng)絡(luò)控制器）
文件頁(yè)數(shù)：	180/671頁(yè)
文件大?。?/td>	2229K
代理商：	ΜPD98501

Preliminary User’s Manual S14767EJ1V0UM00

2.6.4.5 Soft reset exception

A Soft Reset (sometimes called Warm Reset) occurs when the ColdReset_B signal (internal) remains deasserted

while the Reset_B signal (internal) goes from assertion to deassertion (for details, see

Section 2.7 Initialization

A Soft Reset immediately resets all state machines, and sets the SR bit of the Status register. Execution begins at

the reset vector when the reset is deasserted.

This exception is not maskable.

PD98501, a soft reset never occurs.

(2) Processing

The CPU provides a special interrupt vector for this exception (same location as Cold Reset):

0xBFC0 0000 (virtual) in 32-bit mode

0xFFFF FFFF BFC0 0000 (virtual) in 64-bit mode

This vector is located within unmapped and uncached address space, so that the cache and TLB need not be

initialized to process this exception. The SR bit of the Status register is set to 1 to distinguish this exception from a

Cold Reset exception.

When this exception occurs, the contents of all registers are preserved except for the following registers:

When the MIPS16 instruction execution is disabled, the PC value at which an exception occurs is set to the

ErrorEPC register.

When the MIPS16 instruction execution is enabled, the PC value at which an exception occurs is set to the

ErrorEPC register and the ISA mode in which an exception occurs is set to the least significant bit of the

ErrorEPC register.

TS bit of the Status register is cleared to 0.

ERL, SR, and BEV bits of the Status register are set to 1.

During a soft reset, access to the operating cache or system interface may be aborted. This means that the

contents of the cache and memory will be undefined if a Soft Reset occurs.

(3) Servicing

The Soft Reset exception is serviced by:

Preserving the current processor states for diagnostic tests

Reinitializing the system in the same way as for a Cold Reset exception

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