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CHAPTER 6 USB CONTROLLER
432
Preliminary User’s Manual S14767EJ1V0UM00
Numbers (1) to (11) do not indicate the order in which USB Controller must perform processing. Instead, these
numbers correspond to those in the following explanation.
(1)
(2)
USB Controller is in the status where it waits to receive data (USB Packets) from the USB.
USB Controller receives data (USB Packets) from the USB. As it is receiving the data, USB Controller
performs NRZI decoding, CRC check, and Bit Stuffing Error check.
USB Controller stores the received data into the FIFO.
USB Controller checks whether a buffer for storing receive data has been allocated in system memory.
If USB Controller finds that a buffer has not been allocated, it prepares a new buffer.
USB Controller checks whether the buffer prepared in (5) is in a new Buffer Directory.
If USB Controller finds that the buffer is in a new Buffer Directory, USB Controller updates the link pointer
for the Buffer Directory that has been used up to that point. It also updates the Buffer Directory address of
the pool descriptor.
USB Controller then DMA-transfers data from the FIFO to system memory.
USB Controller checks whether the DMA-transferred data is the last data.
(10) If USB Controller finds that the transferred data is in fact the last data, renews the Size field and Last bit of
Buffer Descriptor and writes the Rx indication into the prepared Mailbox.
(11) USB Controller updates the write pointer of the mailbox (Rx MailBox Write Address Register Address:
8CH). Also, it sets the receive completion bit of the USB General Status Register1 and, provided it is not
masked, issues an interrupt to the V
R
4120A RISC Processor.
(3)
(4)
(5)
(6)
(7)
(8)
(9)