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型號(hào)：	μPD98501
廠商：	NEC Corp.
英文描述：	Network Controller(網(wǎng)絡(luò)控制器)
中文描述：	網(wǎng)絡(luò)控制器（網(wǎng)絡(luò)控制器）
文件頁(yè)數(shù)：	176/671頁(yè)
文件大?。?/td>	2229K
代理商：	ΜPD98501

Preliminary User’s Manual S14767EJ1V0UM00

2.6.4 Details of exceptions

This section describes causes, processes, and services of the V

4120A's exceptions.

2.6.4.1 Exception types

This section gives sample exception handler operations for the following exception types:

Remaining processor exceptions

When the EXL and ERL bits in the Status register are 0, either User, Supervisor, or Kernel operating mode is

specified by the KSU bits in the Status register. When either the EXL or ERL bit is set to 1, the processor is in Kernel

When the processor takes an exception, the EXL bit is set to 1, meaning the system is in Kernel mode. After

saving the appropriate state, the exception handler typically resets the EXL bit back to 0. The exception handler sets

the EXL bit to 1 so that the saved state is not lost upon the occurrence of another exception while the saved state is

being restored.

Returning from an exception also resets the EXL bit to 0. For details, see

APPENDIX A MIPS III INSTRUCTION

2.6.4.2 Exception vector address

The Cold Reset, Soft Reset, and NMI exceptions are always branched to the following reset exception vector

address. This address is in an uncached, unmapped space.

0xBFC0 0000 in 32-bit mode (virtual address)

0xFFFF FFFF BFC0 0000 in 64-bit mode (virtual address)

Vector addresses for the remaining exceptions are a combination of a vector offset and a base address.

64-/32-bit mode exception vectors and their offsets are shown below.

Table 2-58. 64-Bit Mode Exception Vector Base Addresses

Vector Base Address (Virtual)

Vector Offset

0xFFFF FFFF BFC0 0000

(BEV bit is automatically set to 1)

TLB Refill (EXL = 0)

XTLB Refill (EXL = 0)

Other exceptions

0xFFFF FFFF 8000 0000 (BEV = 0)

0xFFFF FFFF BFC0 0200 (BEV = 1)

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