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CHAPTER 5 ETHERNET CONTROLLER
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Preliminary User’s Manual S14767EJ1V0UM00
Operation flow for transmit packet
i)
ii) Initializes registers (En_TXDPR, En_TXCR)
iii) Reads buffer descriptor for transmission from SDRAM
iv) Reads transmit data from data buffer by using master DMA burst operation
v) Waits for exceeding of transmit drain threshold (TXDRTH)
Senses carrier
Transmits data (Preamble. SFD, data)
vi) Reads continuous data
If the current buffer descriptor does not show a last packet (L=0), it reads continuous data.
Increments current Transmit Descriptor Pointer
vii) Reads next buffer descriptor
viii)Reads continuous data from data buffer again
ix) Stores the transmit status in the buffer descriptor
x) Generates an interrupt
xi) Reads next buffer descriptor and data, if available
Prepares transmit data in data buffer
5.3.5 Frame reception
The receiver is designed to work with almost no intervention from the host processor and can perform address
recognition, CRC checking and maximum frame length checking.
When the driver enables the receiver by setting Receive Descriptor Pointer Register (En_RXDPR) and Receive
Enable (RXE), it will immediately start processing receive frames. The receiver will first check for a valid preamble
(PA) / start frame delimiter (SFD) header at the beginning packet. If the PA/SFD is valid, it will be stripped and the
frame will be processed by the receiver. If a valid PA/SFD is not found the frame will be ignored.
Once a collision window (64 bytes) of data has been received and if address recognition has not rejected the frame,
Ethernet Controller starts transferring the incoming frame to the receive data buffer. If the frame is a runt (due to
collision) or is rejected by address recognition, no receive buffers are filled. Thus, no collision frames are presented to
the user except late collisions, which indicate serious LAN problems.
It has no matter since after the reception it writes the receive status into the descriptor even if the received data
were gone out to SDRAM.
If the incoming frame exceeds the length of the data buffer, Ethernet Controller fetches the next Receive Descriptor
Buffer in the table and, if it is empty, continues transferring the rest of the frame to this data buffer.
If the remaining number of descriptors is under four times of the alert level, Ethernet Controller generates an interrupt
to request new additional descriptors.
During reception, Ethernet Controller checks for a frame that is either too short or too long. When the frame ends
(carrier sense is negated), the receive CRC field is checked out and written to the data buffer. The data length written
to the last data Buffer in the Ethernet frame is the length of the entire frame. Frames that are less then 64 bytes in
length are not DMA’d (transferred) and, are rejected in hardware with no impact on system bus utilization if the data is
in the Rx FIFO.
Caution
Recommend a high (over 16 words) drain threshold.
When the receive frame is complete, Ethernet Controller sets the L-bit in the Receive Descriptor, writes the frame
status bits into the Receive Descriptor, and sets the OWN-bit. Ethernet Controller generates a maskable interrupt,
indicating that a frame has been received and is in memory. Ethernet Controller then waits for a new frame.
Receive procedure is as follows:(Figure 5-8)