![](http://datasheet.mmic.net.cn/380000/-PD98501_datasheet_16745028/-PD98501_327.png)
CHAPTER 4 ATM CELL PROCESSOR
Preliminary User’s Manual S14767EJ1V0UM00
327
CLP
:Set to 1 if the CLP in the header of at least one cell of the packet being
received is equal to 1.
:Set to 1 if the free buffer assigned to this VC exists.
:Set to 1 if an error occurs while a packet is being received. Then, the
subsequent cells of the packet, including the last cell, are discarded.
:If a free buffer is not assigned, the cell is discarded and this field is set to 1.
:Always 0 because it is not used by ATM Cell Processor.
:Mailbox number.
:Pool number. (ATM Cell Processor supports pool numbers 0 to 7.)
:User information
:Area used for T1 timer calculation
:Congestion notification.
:OAM cell reception/discard indication bit.
:AAL-5/RAW cell reception indication bit.
:Maximum allowable number of segments in one packet
:Number of words of the free area remaining in the current buffer
BFA
RID
DD
DP
MB
POOL NO
UINFO
T1 TIMESTAMP
CI
OD
A/R
MAX.NO.OF SEGMENTS
REMAINING WORDS IN CURRENT
BUFFER
CURRENT COUNT OF SEGMENTS
CRC-32 COUNT
BUFFER WRITE ADDRESS
CURRENT BUFFER POINTER
PACKET START ADDRESS
Tx VC TABLE POINTER
WORD 6 to WORD 12
BACKWARD POINTER
LST
FORWARD POINTER
:Number of segments of the current packet that have been received so far
:Used for CRC-32 value calculation
:Next address in the currently assigned free buffer that is used for storage
:Start address of the free buffer to be assigned next
:Start address of the packet (start address of the batch assigned first)
:Pointer to the Tx VC Table. This field is used in ABR only.
:These fields are used internally for ABR service.
:VC Number of the VC linked before this VC in the T1 link list
:Set to 1 if the VC is the last one linked in the T1 link list.
:VC Number of the VC linked after this VC in the T1 link list
4.8.3.2
Non AAL-5 traffic support
Every time ATM Cell Processor receives raw cell, it makes a raw cell data with 53 byte raw cell and 11 byte
indication and stores it to the appropriate Rx pool. Then, ATM Cell Processor sets corresponding bits in A_GSR
register and generate interruption if not masked.
Since ATM Cell Processor treats raw cells as a unit of cell not a packet, it doesn’t stores rx indications in Rx
mailbox. When ATM Cell Processor receives raw cells, CRC-10 verify function is always enable. If ATM Cell
Processor detects CRC-10 error, sets error bit in raw cell data.
(1) OAM F5 cell
When OD bit in VC table is 1 and PTI field in received ATM cell header is “1xx”, ATM Cell Processor generates
Raw cell data and stores it in pool 0. It sets PCR0=1 in A_GSR register and generates interruption to V
R
4120A RISC
Processor, if not masked. ATM Cell Processor always stores these data in Pool 0. If OD bit is set to 1, Pool 0 has to
be set for Raw cell data.
(2) Non AAL-5 traffic
When A/R bit in VC table is 0, ATM Cell Processor treats cells belongs to the VC as raw cells. If receives raw cells,
ATM Cell Processor has to assign a pool to raw cell data.