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型號(hào)：	μPD98501
廠商：	NEC Corp.
英文描述：	Network Controller(網(wǎng)絡(luò)控制器)
中文描述：	網(wǎng)絡(luò)控制器（網(wǎng)絡(luò)控制器）
文件頁(yè)數(shù)：	171/671頁(yè)
文件大?。?/td>	2229K
代理商：	ΜPD98501

Preliminary User’s Manual S14767EJ1V0UM00

2.6.3.7 Exception program counter (EPC) register (14)

The Exception Program Counter (EPC) is a read/write register that contains the address at which processing

resumes after an exception has been serviced. The contents of this register change depending on whether execution

of MIPS16 instructions is enabled or disabled. Setting the MIPS16EN pin after RTC reset specifies whether execution

of the MIPS16 instructions is enabled or disabled.

When the MIPS16 instruction execution is disabled, the EPC register contains either:

Virtual address of the instruction that caused the exception.

Virtual address of the immediately preceding branch or jump instruction (when the instruction associated with

the exception is in a branch delay slot, and the BD bit in the Cause register is set to 1).

When the MIPS16 instruction execution is enabled, the EPC register contains either:

Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs.

Virtual address of the immediately preceding branch or jump instruction and ISA mode at which an exception

occurs (when the instruction associated with the exception is in a branch delay slot of the jump instruction,

and the BD bit in the Cause register is set to 1).

When the 16-bit instruction is executed, the EPC register contains either:

Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs.

Virtual address of the immediately preceding Extend or jump instruction and ISA mode at which an exception

occurs (when the instruction associated with the exception is in a branch delay slot of the jump instruction or

in the instruction following the Extend instruction, and the BD bit in the Cause register is set to 1).

The EXL bit in the Status register is set to 1 to keep the processor from overwriting the address of the exception-

causing instruction contained in the EPC register in the event of another exception.

Figure 2-64 shows the EPC register format when MIPS16 ISA is disabled, and Figure 2-65 shows the EPC register

format when MIPS16 ISA is enabled.

Figure 2-64. EPC Register Format (When MIPS16 ISA Is Disabled)

(a) 32-bit mode

(b) 64-bit mode

EPC: Restart address after exception processing.

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