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CHAPTER 2 V
R
4120A
140
Preliminary User’s Manual S14767EJ1V0UM00
Kernel mode virtual address space is divided into regions differentiated by the high-order bits of the virtual address,
as shown in Figure 2-40. Table 2-50 lists the characteristics of the 32-bit Kernel mode segments, and Table 2-51 lists
the characteristics of the 64-bit Kernel mode segments.
Figure 2-40. Kernel Mode Address Space
32-bitmode
Note 1
0.5 Gbytes with
TLB mapping
0.5 Gbytes with
TLB mapping
0.5 Gbytes without
TLB mapping
uncacheable
64-bit mode
0xDFFF FFFF
0xE000 0000
0xC000 0000
0xBFFF FFFF
0xFFFF FFFF
0xFFFF FFFF FFFF FFFF
kuseg
kseg0
kseg1
ksseg
kseg3
0x7FFF FFFF
0x0000 0000
0x8000 0000
xkuseg
xksseg
xkphys
xkseg
ckseg0
ckseg1
ckseg
cksseg
0xFFFF FFFF 9FFF FFFF
0xFFFF FFFF A000 0000
0.5 Gbytes without
TLB mapping
cacheable
2 Gbytes with TLB
mapping
0xFFFF FFFF E000 0000
0xFFFF FFFF DFFF FFFF
0xFFFF FFFF C000 0000
0xFFFF FFFF BFFF FFFF
0xFFFF FFFF 7FFF FFFF
0xFFFF FFFF 8000 0000
0xC000 00FF 7FFF FFFF
0xC000 00FF 8000 0000
0.5 Gbytes with
TLB mapping
0.5 Gbytes with
TLB mapping
0.5 Gbytes without
TLB mapping
uncacheable
0.5 Gbytes without
TLB mapping
cacheable
Address error
With TLB mapping
Without TLB mapping
(See Table 6-7 for
details.)
Address error
1 Tbyte with TLB
mapping
Address error
1 Tbyte with TLB
mapping
0x4000 00FF FFFF FFFF
0x4000 0100 0000 0000
0xC000 0000 0000 0000
0xBFFF FFFF FFFF FFFF
0x8000 0000 0000 0000
0x7FFF FFFF FFFF FFFF
0x3FFF FFFF FFFF FFFF
0x4000 0000 0000 0000
0x0000 0000 0000 0000
0x0000 00FF FFFF FFFF
0x0000 0100 0000 0000
0xA000 0000
0x9FFF FFFF
Note 2
Notes 1.
The V
R
4120A uses 64-bit addresses within it. For 32-bit mode addressing, bit 31 is sign-extended to
bits 32 to 63, and the resulting 32 bits are used for addressing. Usually, a 64-bit instruction is used for
the program in 32-bit mode.
The K0 field of the Config register controls cacheability of kseg0 and ckseg0.
2.