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CHAPTER 2 V
R
4120A
110
Preliminary User’s Manual S14767EJ1V0UM00
Table 2-40. Jump and Branch Instructions (2/2)
Instruction
Format and Description
Jump and Link Register
JALR ra, rx
The program unconditionally jumps to the address contained in register rx, with a delay of one
instruction. This instruction sets the ISA Mode bit to the value in rx bit 0. The address of the
instruction immediately following the delay slot is placed in register ra. The value stored in ra bit 0 will
reflect the ISA mode bit before the jump execution is executed.
If the Jump target address is in the MIPS16 instruction length mode, no address exception occurs
when bit 0 of the source register is 1 because bit 0 of the target address is 0 so that the instruction is
located at the halfword boundary.
If the 32-bit length instruction mode is changed, an address exception occurs when the jump target
address is fetched if the two low-order bits of the target address are not 0.
Branch on Equal to
Zero
BEQZ rx, immediate
The 8-bit immediate is shifted left one bit, sign extended, and then added to the address of the
instruction after the branch to form the target address. If the contents of general register rx are equal
to zero, the program branches to the target address. No delay slot is generated.
Branch on Not Equal to
Zero
BNEZ rx, immediate
The 8-bit immediate is shifted left one bit, sign extended, and then added to the address of the
instruction after the branch to form the target address. If the contents of general register rx are not
equal to zero, the program branches to the target address. No delay slot is generated.
Branch on T Equal to
Zero
BTEQZ immediate
The 8-bit immediate is shifted left one bit, sign extended, and then added to the address of the
instruction after the branch to form the target address. If the contents of special register T ($24) are
equal to zero, the program branches to the target address. No delay slot is generated.
Branch on T Not Equal
to Zero
BTNEZ immediate
The 8-bit immediate is shifted left one bit, sign extended, and then added to the address of the
instruction after the branch to form the target address. If the contents of special register T ($24) are
not equal to zero, the program branches to the target address. No delay slot is generated.
Branch Unconditional
B immediate
The 11-bit immediate is shifted left one bit, sign extended, and then added to the address of the
instruction after the branch to form the target address. The program branches to the target address
unconditionally. No delay slot is generated.