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CHAPTER 2 V
R
4120A
Preliminary User’s Manual S14767EJ1V0UM00
85
Table 2-22. General Registers
MIPS16 Register
Encoding
32-Bit MIPS Register
Encoding
Symbol
Comment
0
16
s0
General register
1
17
s1
General register
2
2
v0
General register
3
3
v1
General register
4
4
a0
General register
5
5
a1
General register
6
6
a2
General register
7
7
a3
General register
N/A
24
t8
MIPS16 condition code register. BTEQZ, BTNEZ, CMP,
CMPI, SLT, SLTU, SLTI, and SLTIU instructions are
implicitly referenced.
N/A
29
sp
Stack pointer register
N/A
31
ra
Return address register
Remarks 1.
The symbols are the general assembler symbols.
2.
The MIPS register encoding numbers 0 to 7 correspond to the MIPS16 binary encoding of the
registers, and are used to show the relationship between this encoding and the MIPS registers. The
numbers 0 to 7 are not used to reference registers, except within binary MIPS16 instructions.
Registers are referenced from the assembler using the MIPS name ($16, $17, $2, etc.) or the
symbol name (s0, s1, v0, etc.). For example, when register number 17 is accessed with the register
file, the programmer references either $17 or s1 even if the MIPS16 encoding of this register is 001.
3.
The general registers not shown in this table cannot be accessed with a MIPS16 instruction set
other than the Move instruction. The Move instruction of MIPS16 can access all 32 general
registers.
4.
To reference the MIPS16 condition code registers with this manual, either T, t8, or $24 has to be
used, depending on the case. These three names reference the same physical register.
Table 2-23. Special Registers
Symbol
Description
PC
Program counter. The PC-relative Add instruction and Load instruction can
access this register.
HI
The upper word of the multiply or divide result is inserted
LO
The lower word of the multiply or divide result is inserted