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型號(hào)：	μPD98501
廠商：	NEC Corp.
英文描述：	Network Controller(網(wǎng)絡(luò)控制器)
中文描述：	網(wǎng)絡(luò)控制器（網(wǎng)絡(luò)控制器）
文件頁(yè)數(shù)：	58/671頁(yè)
文件大?。?/td>	2229K
代理商：	ΜPD98501

Preliminary User’s Manual S14767EJ1V0UM00

4120A instruction set overview

For CPU instructions, there are two types of instructions – 32-bit length instruction (MIPS III) and 16-bit length

instruction (MIPS16).

2.1.3.1 MIPS III instruction

All the CPU instructions are 32-bit length when executing MIPS III instructions, and they are classified into three

instruction formats as shown in Figure 2-3: immediate (I-type), jump (J-type), and register (R-type). The field of each

instruction format is described in

Section 2.2 MIPS III Instruction Set Summary

Figure 2-3. CPU Instruction Formats (32-bit Length Instruction)

I-type (immediate)

J-type (jump)

R-type (register)

The instruction set can be further divided into the following five groupings:

(a) Load and store instructions move data between memory and general-purpose registers. They are all

immediate (I-type) instructions, since the only addressing mode supported is base register plus 16-bit, signed

immediate offset.

(b) Computational instructions perform arithmetic, logical, shift, and multiply and divide operations on values in

registers. They include R-type (in which both the operands and the result are stored in registers) and I-type

(in which one operand is a 16-bit signed immediate value) formats.

address formed by combining a 26-bit target address with the high-order bits of the Program Counter (J-type

format) or register address (R-type format). The format of the branch instructions is I type. Branches have

16-bit offsets relative to the Program Counter. JAL instructions save their return address in register 31.

(d) Coprocessor 0 (System Control Coprocessor, CP0) instructions perform operations on CP0 registers to

control the memory-management and exception-handling facilities of the processor.

(e) Special instructions perform system calls and breakpoint operations, or cause a branch to the general

exception-handling vector based upon the result of a comparison. These instructions occur in both R-type

and I-type formats.

For the operation of each instruction, refer to

Section 2.2 MIPS III Instruction Set Summary

MIPS III INSTRUCTION SET DETAILS

2.1.3.2 MIPS16 instruction

All the CPU instructions except for JAL and JALX are 16-bit length when executing MIPS16 instructions, and they

are classified into thirteen instruction formats as shown in Figure 2-4.

The field of each instruction format is described in

Section 2.3 MIPS16 Instruction Set

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