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CHAPTER 4 ATM CELL PROCESSOR
Preliminary User’s Manual S14767EJ1V0UM00
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4.4.12 A_MTA0-A_MTA3 (Mailbox Tail Address Register)
A_MTA0-A_MTA3 shows tail address of Receive Mailbox (Mailbox0 and Mailbox1) and Transmit Mailbox
(Mailbox2 and Mailbox3) respectively. Initial value is zero.
A_MTA0[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
A_MTA1[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
A_MTA2[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
A_MTA3[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
4.4.13 A_MWA0-A_MWA3 (Mailbox Write Address Register)
A_MWA0-A_MWA3 shows write address of Receive Mailbox (Mailbox0 and Mailbox1) and Transmit Mailbox
(Mailbox2 and Mailbox3) respectively. Initial value is zero.
A_MWA0[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
A_MWA1[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
A_MWA2[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
A_MWA3[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
4.4.14 A_RCC (Valid Receive Cell Counter Register)
A_RCC counts the number of valid Receive cells. It is a 32-bit free-run counter. Overflow of this counter does NOT
cause any interruption. Initial value is zero.
A_RCC[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
4.4.15 A_TCC (Valid Transmit Cell Counter Register)
A_TCC counts the number of valid Transmit cells. It is a 32-bit free-run counter. Overflow of this counter does NOT
cause any interruption. Initial value is zero.
A_TCC[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0