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CHAPTER 1 INTRODUCTION
Preliminary User’s Manual S14767EJ1V0UM00
47
1.8 I/O Register Map
Core
Offset
Register
Length
(Byte)
4
4
4
4
4
-
4
-
4
-
4
-
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
4
-
4
-
4
-
4
4
-
4
-
-
-
4
4
4
4
4
4
-
4
-
4
4
4
-
4
4
-
4
4
4
4
4
-
4
4
-
Name
Access by
V
R
4120A
Description
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
ATM
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
F000H
F004H
F008H
F00CH
F010H
F014H
F018H
F01CH
F020H
F024H
F028H
F02CH-F04CH
F050H
F054H
F058H
F05CH
F060H
F064H
F068H
F06CH
F070H
F074H
F078H
F07CH
F080H
F084H
F088H
F08CH
F090H
F094H
F098H
F09CH
F0A0H-F0AFH
F0B0H-F0B3H
F0B4H-F0BCH
F0C0H
F0C4H
F0C8H
F200H-F2FFH
F300H
F304H
F308H- F31FH
F320H
F324H- F3FFH
F400H-F4FFH
F500H-FFFFH
00H
04H
08H
0CH
10H
14H
18H-1CH
20H
24H-50H
54H
58H
5CH
60H
64H
80H
84H-90H
94H
98H
9CH
A0H
A4H
A8H-C4H
CCH
D0H
D4H-D8H
A_GMR
A_GSR
A_IMR
A_RQU
A_RQA
N/A
A_VER
N/A
A_CMR
N/A
A_CER
N/A
A_MSA0
A_MSA1
A_MSA2
A_MSA3
A_MBA0
A_MBA1
A_MBA2
A_MBA3
A_MTA0
A_MTA1
A_MTA2
A_MTA3
A_MWA0
A_MWA1
A_MWA2
A_MWA3
A_RCC
A_TCC
A_RUEC
A_RIDC
N/A
A_APR
N/A
A_T1R
N/A
A_TSR
N/A
A_IBBAR
A_INBAR
N/A
A_UMCMD
N/A
N/A
N/A
En_MACC1
En_MACC2
En_IPGT
En_IPGR
En_CLRT
En_LMAX
N/A
En_RETX
N/A
En_LSA2
En_LSA1
En_PTVR
N/A
En_VLTP
En_MIIC
N/A
En_MCMD
En_MADR
En_MWTD
En_MRDD
En_MIND
N/A
En_HT1
En_HT2
N/A
R/W
R
R/W
R
R
-
R
-
R/W
-
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
-
R/W
-
R/W
-
R/W
-
R/W
R/W
-
R/W
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
-
R/W
R/W
R
-
R/W
R/W
-
W
R/W
R/W
R
R
-
R/W
R/W
-
General Mode Register
General Status Register
Interrupt Mask Register
Receive Queue Underrunning
Receive Queue Alert
Reserved for future use
Version Number
Reserved for future use
Command Register
Reserved for future use
Command Extension Register
Reserved for future use
Mailbox0 Start Address
Mailbox1 Start Address
Mailbox2 Start Address
Mailbox3 Start Address
Mailbox0 Bottom Address
Mailbox1 Bottom Address
Mailbox2 Bottom Address
Mailbox3 Bottom Address
Mailbox0 Tail Address
Mailbox1 Tail Address
Mailbox2 Tail Address
Mailbox3 Tail Address
Mailbox0 Write Address
Mailbox1 Write Address
Mailbox2 Write Address
Mailbox3 Write Address
Valid Receiving Cell Counter
Valid Transmitting Cell Counter
Receive Unprovisioned VPI/VCI Error Cell Counter
Receiving Internal Discarded Cell Counter
Reserved for future use
ABR Parameter Register
Reserved for future use
T1 Timer Register
Reserved for future use
Time Stamp Register
Can not access from V
R
4120A RISC Core.
IBUS Base Address Register
Instruction Base Address Register
Reserved for future use
UTOPIA Management Interface Command Register
Reserved for future use
Can not access from V
R
4120A RISC Core.
Reserved for future use
MAC configuration register 1
MAC configuration register 2
Back-to-Back IPG register
Non Back-to-Back IPG register
Collision register
Max packet length register
Reserved for future use
Retry count register
Reserved for future use
Station Address register 2
Station Address register 1
Pause timer value read register
Reserved for future use
VLAN type register
MII configuration register
Reserved for future use
MII command register
MII address register
MII write data register
MII read data register
MII indicator register
Reserved for future use
Hash table register 1
Hash table register 2
Reserved for future use