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CHAPTER 6 USB CONTROLLER
Preliminary User’s Manual S14767EJ1V0UM00
385
6.2.2.9
USB EP2 Control Register (U_EP2CR): 28H
31
16
15
0
Reserved
Reserved
30
18
19
EP2EN
MAXP2
9
10
20
21
Reserved
RM2
Register for setting the operation of EndPoint2.
If the value in the MAXP field is rewritten during a send or receive operation, the operation of USB Controller may
become unpredictable. Therefore the MAXP can be written to once only, when initial setting is being performed.
Bit
Field
Description
R/W
31
EP2EN
(EndPoint Enable)
If the V
R
4120A RISC Processor sets this bit to 1, EndPoint2 is enabled for
transmitting and receiving data from and to USB.
R/W
30-20
Reserved
Reserved for future use
R
20-19
RM2
(Rx Mode)
Bit for setting the receive mode.
When this bit is set to 00 or 01, receiving is performed in Normal Mode.
When this bit is set to 10, receiving is performed in Assemble Mode.
When this bit is set to 11, receiving is performed in Separate Mode.
For a detailed explanation of the receive modes, see Section 6.6.4.
R/W
18-10
Reserved
Reserved for future use
R
9-0
MAXP2
(MAX Packet size)
Register that stores the Max Packet Size of EndPoint2. Prior to the start of
a USB transaction, the V
R
4120A RISC Processor must write an appropriate
value into this register.
When this field contains 0, no transaction is performed at EndPoint2.
R/W