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CHAPTER 1 INTRODUCTION
30
Preliminary User’s Manual S14767EJ1V0UM00
1.5.3 System controller
System controller is
μ
PD98501’s internal system controller. System controller provides bridging function among the
V
R
4120A System Bus “SysAD”, NEC original high speed on-chip bus “IBUS” and memory bus for
SDRAM/PROM/FLASH.
Features of System controller are as follows;
Implements 4word prefetch FIFO buffer between SysAD and Memory
Implements 32bit×64word FIFO buffer for each TX and RX to IBUS
Implements 32bit× 4word FIFO buffer for each TX and RX to HBUS
Provides bus bridging function among SysAD bus and IBUS(internal bus) and MEMORY
Supports Endian Converting function on SysAD bus
Can directly connect 16Mbit/64Mbit SDRAM(MAX.32MBytes) and PROM/FLASH(MAX.8MBytes) memory
Supports all V
R
4120A bus cycles at 66MHz or 100MHz
PROM/FLASH data signals multiplexed on SDRAM data signals
Supports 266 MB/sec (32bit @66MHz) bursts on IBUS
Generates NMI and INT
Supports NS16550 compatible Universal Asynchronous Receiver/Transmitter(UART)
Supports separated 2ch Timer
Supports Deadmans Switch Unit(Watch Dog Timer)
Supports Micro Wire interface
Figure 1-5. Block Diagram of System Controller
System Controller
IBUS
SysAD BUS
PBUS-HBUS Bridge
PHB
PBUS-HBUS Bridge
FAST-UART
PFUR
FAST-UART
HBUS Arbiter
HARB
HBUS Arbiter
IBUS-HBUS Bridge
IHB
IBUS-HBUS Bridge
FLASH
PROM
SDRAM
RS232C/Micro Wire
HBUS
HBUS
HBUS
PBUS
ROM-IF
SDRAM-IF
SDRAM-IF
Bridge
System
Bridge
Arbitor
Memory
Arbitor
HBUS
MIF
HIF
VRIF
DSU
DSU
TIMER
TIMER
REGISTER
REGISTER