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CHAPTER 4 ATM CELL PROCESSOR
278
Preliminary User’s Manual S14767EJ1V0UM00
(2/2)
Address
Note
Register
Description
Read/Write
F068H
A_MBA2
Mailbox2 Bottom Address
R/W
F06CH
A_MBA3
Mailbox3 Bottom Address
R/W
F070H
A_MTA0
Mailbox0 Tail Address
R/W
F074H
A_MTA1
Mailbox1 Tail Address
R/W
F078H
A_MTA2
Mailbox2 Tail Address
R/W
F07CH
A_MTA3
Mailbox3 Tail Address
R/W
F080H
A_MWA0
Mailbox0 Write Address
R/W
F084H
A_MWA1
Mailbox1 Write Address
R/W
F088H
A_MWA2
Mailbox2 Write Address
R/W
F08CH
A_MWA3
Mailbox3 Write Address
R/W
F090H
A_RCC
Valid Receiving Cell Counter
R
F094H
A_TCC
Valid Transmitting Cell Counter
R
F098H
A_RUEC
Receive Unprovisioned VPI/VCI Error Cell Counter
R
F09CH
A_RIDC
Receiving Internal Discarded Cell Counter
R
F0A0H-F0ACH
N/A
Reserved for future use
-
F0B0H
A_APR
ABR Parameter Register
R/W
F0B4H-F0BCH
N/A
Reserved for future use
F0C0H
A_T1R
T1 Timer Register
R/W
F0C4H
N/A
Reserved for future use
-
F0C8H
A_TSR
Time Stamp Register
R/W
F200H-F2FFH
N/A
Can not access from V
R
4120A RISC Core.
These register use only internal DMAC.
-
F300H
A_IBBAR
IBUS Base Address Register
R/W
F304H
A_INBAR
Instruction Base Address Register
R/W
F308H- F31FH
N/A
Reserved for future use
-
F320H
A_UMCMD
UTOPIA Management Interface Command Register
R/W
F324H- F3FFH
N/A
Reserved for future use
-
F400H-F4FFH
N/A
Can not access from V
R
4120A RISC Core.
These register use only internal SAR FIFO.
-
F500H-FFFFH
N/A
Reserved for future use
-
Note
V
R
4120A RISC Processor memory space, add 1001_0000H as Base Address.