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CHAPTER 4 ATM CELL PROCESSOR
Preliminary User’s Manual S14767EJ1V0UM00
267
4.1.2.1 RISC core
This block is RISC micro-controller. Its features are as follows:
High performance 32-bit RISC micro-controller, 76MIPS @ 66MHz
32x32-bit General Purpose Registers
32-bit ALU, 32-bit Shifter, 16x16 Multiply-Adder
1KB Data RAM, 8KB Instruction RAM, 8KB Instruction Cache
4.1.2.2 Peripherals
Interrupt Controller (INTC) and Interrupt Edge Detector (INTEDGE)
Peripherals for ATM – Scheduling Table, Rx Lookup Table, IP Lookup Table, and Cell Timer
4.1.2.3 UTOPIA bus controller
This block has some H/W resources - DMA controller, FIFOs, CRC calculators/checkers - inside, and realizes “SW-
SAR” being controlled by F/W on RISC Core. Its features are as follows:
Scatter/Gather-DMA controller which can operate the distributed datum according to descriptor tables, without
F/W help
This DMA controller use for each transmission and reception.
For the improvement of the performance, UTOPIA Bus Controller has the scatter/gather-DMA controllers, which
can handle distributed datum without F/W helps. This DMA controller can write datum to distributed areas
(scattering) and read datum from distributed areas (gathering), according to descriptor tables. Normal DMA
mode is also supported.
Furthermore This DMA controller updates the information related to the DMA operations in VC table in Work
RAM.
Internal BUS interface(IBUS)
External memory interface
32-bit bus interface that can be directly connected to the RISC Core
ATM Zero-padding
Zero-padding is often required to make ATM cells. This block has the circuits for the padding. Only giving the
source address and the number of bytes to be padded, this block pads “0” as desired.
66MHz clock
Transmission and reception SAR FIFO consisting of four cells each