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CHAPTER 3 SYSTEM CONTROLLER
240
Preliminary User’s Manual S14767EJ1V0UM00
3.4 Memory Interface
The CPU accesses memory attached to the controller in the normal way, by addressing the memory space.
3.4.1 Overview
66MHz or 100MHz memory bus.
Up to 32MB Base memory range supports SDRAM.
Up to 8MB write-protectable Boot memory range supports PROM/FLASH.
On-chip programmable SDRAM refresh controller.
4word (16byte) Prefetch data buffer (Memory-to-CPU).
PROM/FLASH data signals multiplexed on SDRAM data signals.
Programmable memory bus arbitration priority.
Programmable address ranges for the memory.
Programmable RAS-CAS delay (2,3,4 clock).
Programmable CAS latency (2,3 clock).
3.4.2 Memory regions and devices
The controller connects directly to memory and manages the addresses, data and control signals for the following
address ranges:
One Boot PROM/FLASH range (programmable)
One System Memory range (programmable)
The following types of memory modules as an example but not limited to, can be used:
FLASH can be used in the Boot ROM.
PROM can be used in the Boot ROM.
16Mbit/64Mbit/128Mbit SDRAM can be used in the system memory.
Boot ROM can be populated with PROM or 85-ns FLASH chips. Prior to accessing PROM/FLASH, software must
configure this address range. The system memory can be populated with 16Mbit/64Mbit/128Mbit SDRAM chips. The
system memory is used for the RTOS, M/W and F/W. Prior to accessing SDRAM, software must configure this
address range.
Recommended SDRAM Devices are listed following:
16Mbit SDRAM (NEC part numbers
μ
PD4516161).
64Mbit SDRAM (NEC part numbers
μ
PD4564323,
μ
PD4564163).
128Mbit SDRAM (NEC part numbers
μ
PD45128163).
Recommended FLASH Devices are listed following:
4Mbit FLASH (NEC part numbers
μ
PD29F800AL).
16Mbit FLASH (NEC part numbers
μ
PD29F1600AL).