![](http://datasheet.mmic.net.cn/380000/-PD98501_datasheet_16745028/-PD98501_92.png)
CHAPTER 2 V
R
4120A
92
Preliminary User’s Manual S14767EJ1V0UM00
EXT-RRI-A instruction format
EXT-SHIFT instruction format
Note
Only in the case of DSLL, the S5 bit is the most significant bit of the 6-bit shift count field (shamt).
In the case of all 32-bit extended shifts, S5 must be 0. For a normal shift instruction, the display of shift
count 0 is considered as shift count 8, but the extended shift instruction does not perform such mapping
changes. Therefore, 0-bit shift using the extended format is possible.
EXT-I8 instruction format
EXT-I64 instruction format
EXT-RI64 instruction format
EXT-SHIFT64 instruction format
Note
The S5 bit is the most significant bit of the 6-bit shift count field (shamt). In the case of a normal shift
instruction, the display of shift count 0 is considered as shift count 8, but the extended shift instruction does
not perform such mapping changes.
Therefore, 0-bit shift using the extended format is possible.
15 14 13 12 11 10
21
20 19 18 17 16
A
27 26 25 24 23 22
31 30 29 28
9
8
7
imm 14:11
immediate 10:4
EXTEND
RRI-A
rx
ry
F
imm 3:0
6
5
4
3
2
1
0
15 14 13 12 11 10
21
20 19 18 17 16
27 26 25 24 23 22
31 30 29 28
9
8
7
S5
Note
shamt 4:0
0
0
0
0
0
EXTEND
SHIFT
rx
ry
0
0
0
F
6
5
4
3
2
1
0
15 14 13 12 11 10
21 20 19 18 17 16
27 26 25 24 23 22
31 30 29 28
9
8
7
immediate 10:5
immediate 15:11
immediate 4:0
EXTEND
l8
Funct
0
0
0
6
5
4
3
2
1
0
15 14 13 12 11 10
21 20 19 18 17 16
27 26 25 24 23 22
31 30 29 28
9
8
7
immediate 10:5
immediate 15:11
immediate 4:0
EXTEND
l64
Funct
0
0
0
6
5
4
3
2
1
0
15 14 13 12 11 10
21 20 19 18 17 16
27 26 25 24 23 22
31 30 29 28
9
8
7
immediate 10:5
immediate 15:11
immediate 4:0
EXTEND
l64
Funct
ry
6
5
4
3
2
1
0
S5
Note
15 14 13 12 11 10
21 20 19 18 17 16
27 26 25 24 23 22
31 30 29 28
9
8
7
shamt 4:0
0
0
0
0
0
Function
EXTEND
RR
0
0
0
ry
6
5
4
3
2
1
0