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CHAPTER 4 ATM CELL PROCESSOR
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Preliminary User’s Manual S14767EJ1V0UM00
4.7 Commands
ATM Cell Processor provides V
R
4120A RISC Processor with the following commands.
Table 4-3. Commands
Command
What this block does
Set_Link_Rate
Set Phy Link Rate
Open_Channel
Reserves VC table area in Work RAM.
Close_Channel
Releases VC table area.
Open_IP_Channel
Reserves Flow Table area in Work RAM
Close_IP_Channel
Releases Flow Table area.
Tx_Ready
Starts transmission process.
IP_Flow_Ready
Starts IP flow transmission process
Add_Buffers
Add Buffer Directories to the indicated pool
Indirect_Access
Enables V
R
4120A RISC Processor to access Work
RAM
Set_Rx_Congestion
(ABR) Set CI bit to 1 for all BRM cells
BRM_Tx
(ABR) Transmit out-of-rate BRM cell
All commands are written in command register (A_CMR) and command extended register (A_CER) by V
R
4120A
RISC Processor. Command register has busy flag. Since ATM Cell Processor only proceeds one command at a time,
it sets the busy flag when it accepts the command. V
R
4120A RISC Processor cannot issue another command while
this busy flag is 1. When finish the command operation, ATM Cell Processor sets the busy flag to 0. V
R
4120A RISC
Processor has to reads the busy flag of the command register and checks if busy bit is 0, before issues new command.
(1) Commands which ATM Cell Processor returns command indication
When ATM Cell Processor receives Open_Channel, Close_Channel, Open_IP_Channel, Close_IP_Channel,
Tx_Ready and Add_Buffers command, it writes command indication in command register. V
R
4120A RISC
Processor has to read command indication, after issuing these commands. However, while busy flag is 1,
ATM Cell Processor has not finished command processing yet, so that, V
R
4120A RISC Processor has to wait
until busy flag in command register becomes 0 in order to read indication.
(2) Commands which command extended register is used
Indirect_Access command, Add_Buffers command and Tx_Ready command with IPoA mode uses command
extended register.
When V
R
4120A RISC Processor writes these commands, V
R
4120A RISC Processor has to write command
extended register first, and then command register. ATM Cell Processor starts command operation when
command register is written. So that, unless command extended register is written first, the information in
command extended register is ignored by ATM Cell Processor.
When command extended register is used for getting information from ATM Cell Processor, V
R
4120A RISC
Processor writes command register and wait until busy flag in command register becomes 0, and reads command
extended register.