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CHAPTER 6 USB CONTROLLER
380
Preliminary User’s Manual S14767EJ1V0UM00
(2/2)
Bit
Field
Description
R/W
8
EP1FU
(EP1 FIFO Error)
Bit that indicates that an underrun has occurred for the FIFO of EndPoint1
(Isochronous IN). If the FIFO empties while EndPoint1 is performing a
transaction,
USB Controller sends an NAK handshaking packet, instead of a data
packet, to the Host PC. Should this occur, this bit is set to 1.
This bit is reset to 0 when the V
R
4120A RISC Processor performs a read.
R/Clear
7
EP6RF
(EP6 Rx Finished )
Bit that indicates that EndPoint6 (Interrupt OUT) has completed the
receiving of a data segment.
This bit is reset to 0 when the V
R
4120A RISC Processor performs a read.
R/Clear
6
EP5TF
(EP5 Tx Finished)
Bit that indicates that EndPoint5 (Interrupt IN) has completed the sending of
a data segment. This bit is reset to 0 when the V
R
4120A RISC Processor
performs a read.
R/Clear
5
EP4RF
(EP4 Rx Finished)
Bit that indicates that EndPoint4 (Bulk OUT) has completed the receiving of
a data segment.
The timing when this bit will be set varies with Rx Mode.
This bit is reset to 0 when the V
R
4120A RISC Processor performs a read.
R/Clear
4
EP3TF
(EP3 Tx Finished)
Bit that indicates that EndPoint3 (Bulk IN) has completed the sending of a
data segment.
This bit is reset to 0 when the V
R
4120A RISC Processor performs a read.
R/Clear
3
EP2RF
(EP2 Rx Finished)
Bit that indicates that EndPoint2 (Isochronous OUT) has completed the
receiving of a data segment.
The timing when this bit will be set varies with Rx Mode.
This bit is reset to 0 when the V
R
4120A RISC Processor performs a read.
R/Clear
2
EP1TF
(EP1 Tx Finished)
Bit that indicates that EndPoint1 (Isochronous IN) has completed the
sending of a data segment. This bit is reset to 0 when the V
R
4120A RISC
Processor performs a read.
R/Clear
1
EP0RF
(EP0 Rx Finished)
Bit that indicates that EndPoint0 (Control) has completed the receiving of a
data segment. This bit is reset to 0 when the V
R
4120A RISC Processor
performs a read.
R/Clear
0
EP0TF
(EP0 Tx Finished)
Bit that indicates that EndPoint0 (Control) has completed the sending of a
data segment.
This bit is reset to 0 when the V
R
4120A RISC Processor performs a read.
R/Clear