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CHAPTER 6 USB CONTROLLER
Preliminary User’s Manual S14767EJ1V0UM00
411
6.4.1 Receive pool setting
For details of the receive pool setting, see Section 6.6.3.
6.4.2 Send/receive mailbox setting
After USB Controller sends a data segment, it indicates the status by writing a send indication into system memory.
The area into which an indication is written is called a "mailbox," and exists within the system memory. As part of
initialization, the V
R
4120A RISC Processor must set the mailboxes. USB Controller uses the mailboxes as a buffer
having a ring configuration in system memory. This buffer is set using four registers for each of sending and receiving.
Registers for setting a send mailbox
TMSA (USB Tx MailBox Start Address Register:
TMBA (USB Tx MailBox Bottom Address Register: 74H)
TMRA (USB Tx MailBox Read Address Register:
TMWA (USB Tx MailBox Write Address Register:
70H)
78H)
7CH)
Registers for setting a receive mailbox
RMSA (USB Rx MailBox Start Address Register:
RMBA (USB Rx MailBox Bottom Address Register: 84H)
RMRA (USB Rx MailBox Read Address Register:
RMWA (USB Rx MailBox Write Address Register: 8CH)
80H)
88H)
Remarks 1.
At initialization, TMRA must be set to the same value as TMSA. Similarly, RMRA must be set to
the same value as RMSA.
2.
When V
R
4120A RISC Processor writes the value to TMSA firstly after reset, USB Controller
automatically copies the value to TMWA internally. Similarly, when V
R
4120A RISC Processor
writes the value to RMSA firstly after reset, USB Controller automatically copies the value to
RMWA internally.
3.
Do not set the same values for TMSA and TMBA.
4.
Among those registers used to set the mailboxes, the V
R
4120A RISC Processor updates only
TMRA and RMRA. The other registers are written to only as part of initialization. They are not to
be written to at any other time.
5.
Each receive indication has a two-word configuration. Therefore, the size of the receive mailbox
must be an integer multiple of two words.
The configuration of the mailboxes in system memory is as shown in the following figure 6-3.