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CHAPTER 1 INTRODUCTION
Preliminary User’s Manual S14767EJ1V0UM00
49
Core
Offset
Register
Length
(Byte)
-
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
4
4
4
4
4
-
4
4
4
4
4
4
4
4
4
4
-
4
4
-
-
4
4
4
4
4
4
4
4
4
4
4
-
4
4
4
-
4
4
4
4
4
4
-
-
4
4
4
4
4
4
Name
Access by
V
R
4120A
Description
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
54H-7FH
80H
80H
80H
84H
84H
88H
88H
8CH
90H
94H
98H
9CH
A0H
A4H
A8H
ACH
B0H
B4H
B8H
BCH
C0H
C4H-CFH
D0H
D4H
D8H
DCH
E0H
E4H-FFH
100H
104H
108H
10CH
110H
114H
118H
11CH
120H
124H
128H-FFFH
0x00
0x04
0x08
0x0c
0x10
0x14
0x18
0x1c
0x20
0x24
0x28
0x2c
0x30
0x34
0x38
0x3c
0x40
0x44
0x48
0x4c
0x50
0x54
0x58
0x5c
0x60
0x64
0x68
0x6c
0x70
0x74
0x78
0x7c
0x80
0x84
N/A
UARTDLL
UARTRBR
UARTTHR
UARTDLM
UARTIER
UARTFCR
UARTIIR
UARTLCR
UARTMCR
UARTLSR
UARTMSR
UARTSCR
DSUCNTR
DSUSETR
DSUCLRR
DSUTIMR
TMMR
TM0CSR
TM1CSR
TM0CCR
TM1CCR
N/A
ECCR
ERDR
MACAR1
MACAR2
MACAR3
N/A
RMMDR
RMATR
SDMDR
SDTSR
SDPTR
SDRMR
SDRCR
SDRMR
SDRCR
MBCR
N/A
U_GMR
U_VER
N/A
N/A
U_GSR1
U_IMR1
U_GSR2
U_IMR2
U_EP0CR
U_EP1CR
U_EP2CR
U_EP3CR
U_EP4CR
U_EP5CR
U_EP6CR
N/A
U_CMR
U_CA
U_TEPSR
N/A
U_RP0IR
U_RP0AR
U_RP1IR
U_RP1AR
U_RP2IR
U_RP2AR
N/A
N/A
U_TMSA
U_TMBA
U_TMRA
U_TMWA
U_RMSA
U_RMBA
-
R/W
R
W
R/W
R/W
W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R
R
-
W
R
R
R
R
-
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R
R/W
-
R/W
R
R/W
R
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
-
R/W
R
R/W
R
R/W
R
-
-
R/W
R/W
R/W
R
R/W
R/W
Reserved
UART, Divisor Latch LSB Register [DLAB=1]
UART, Receiver Buffer Register [DLAB=0,READ]
UART, Transmitter Holding Register [DLAB=0,WRITE]
UART, Divisor Latch MSB Register [DLAB=1]
UART, Interrupt Enable Register [DLAB=0]
UART, FIFO control Register [WRITE]
UART, Interrupt ID Register [READ]
UART, Line control Register
UART, Modem Control Register
UART, Line status Register
UART, Modem Status Register
UART, Scratch Register
DSU Control Register
DSU Dead Time Set Register
DSU Clear Register
DSU Elapsed Time Register
Timer Mode Register
Timer CH0 Count Set Register
Timer CH1 Count Set Register
Timer CH0 Current Count Register
Timer CH1 Current Count Register
Reserved
EEPROM
Command Control Register
EEPROM Read Data Register
MAC Address Register 1
MAC Address Register 2
MAC Address Register 3
Reserved
Boot ROM Mode Register
Boot ROM Access Timing Register
SDRAM Mode Register
SDRAM Type Selection Register
SDRAM Precharge Timing Register
SDRAM Precharge Mode Register
SDRAM Precharge Timer Count Register
SDRAM Refresh Mode Register
SDRAM Refresh Timer Count Register
Memory Bus Control Register
Reserved
USB General Mode Register
USB Frame number/Version Register
Reserved for future use
Reserved for future use
USB General Status Register 1
USB Interrupt Mask Register 1
USB General Status Resister 2
USB Interrupt Mask Register 2
USB EP0 Control Register
USB EP1 Control Register
USB EP2 Control Register
USB EP3 Control Register
USB EP4 Control Register
USB EP5 Control Register
USB EP6 Control Register
Reserved for future use
USB Command Register
USB Command Address Register
USB Tx EndPoint Status Register
Reserved for future use
USB Rx Pool0 Information Register
USB Rx Pool0 Address Register
USB Rx Pool1 Information Register
USB Rx Pool1 Address Register
USB Rx Pool2 Information Register
USB Rx Pool2 Address Register
Reserved for future use
Reserved for future use
USB Tx MailBox Start Address Register
USB Tx MailBox Bottom Address Register
USB Tx MailBox Read Address Register
USB Tx MailBox Write Address Register
USB Rx MailBox Start Address Register
USB Rx MailBox Bottom Address Register