![](http://datasheet.mmic.net.cn/380000/-PD98501_datasheet_16745028/-PD98501_50.png)
CHAPTER 1 INTRODUCTION
50
Preliminary User’s Manual S14767EJ1V0UM00
Core
Offset
Register
Length
(Byte)
4
4
-
4
4
-
-
4
-
-
-
4
4
4
4
4
4
4
-
-
4
4
4
-
-
4
4
-
-
4
-
-
-
4
4
4
4
4
4
4
-
4
4
-
-
4
-
-
-
4
4
4
4
4
4
4
-
Name
Access by
V
R
4120A
Description
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
0x88
0x8c
0x90-0xff
0x100
0x104
0x108
0x10c
0x110
0x114
0x118
0x11c
0x120
0x124
0x128
0x12c
0x130
0x134
0x138
0x13c
0x140-15f
0x160
0x164
0x168
0x16c
0x170-17f
0x180
0x184
0x188
0x18c
0x190
0x194
0x198
0x19c
0x1a0
0x1a4
0x1a8
0x1ac
0x1b0
0x1b4
0x1b8
0x1bc
0x1c0
0x1c4
0x1c8
0x1cc
0x1d0
0x1d4
0x1d8
0x1dc
0x1e0
0x1e4
0x1e8
0x1ec
0x1f0
0x1f4
0x1f8
0x1fc
U_RMRA
U_RMWA
N/A
U_TDN
U_TDS
N/A
N/A
U_THT
N/A
N/A
N/A
U_RDT
U_RDCER
U_RDBER
U_RDTER
U_RHT
U_RHN
U_RHS
N/A
N/A
U_DT2
U_DCER2
U_DBER2
N/A
N/A
U_DN3
U_DS3
N/A
N/A
U_HT3
N/A
N/A
N/A
U_DT4
U_DCER4
U_DBER4
U_DTER4
U_HT4
U_HN4
U_HS4
N/A
U_DN5
U_DS5
N/A
N/A
U_HT5
N/A
N/A
N/A
U_DT6
U_DCER6
U_DBER6
U_DTER6
U_HT6
U_HN6
U_HS6
N/A
R/W
R
-
R
R
-
-
R
-
-
-
R
R
R
R
R
R
R
R
-
R
R
R
-
-
R
R
-
-
R
-
-
-
R
R
R
R
R
R
R
-
R
R
-
-
R
-
-
-
R
R
R
R
R
R
R
-
USB Rx MailBox Read Address Register
USB Rx MailBox Write Address Register
Reserved for future use
USB EP0 Tx Data Phase NAK Counter
USB EP0 Tx Data Phase STALL Counter
Reserved for future use
Reserved for future use
USB EP0 Tx Handshake Phase Timeout Counter
Reserved for future use
Reserved for future use
Reserved for future use
USB EP0 Rx Data Phase Timeout Counter
USB EP0 Rx Data Phase CRC Error Counter
USB EP0 Rx Data Phase Bitstuff Error Counter
USB EP0 Rx Data Phase Data Toggle Error Counter
USB EP0 Rx Handshake Phase Timeout Counter
USB EP0 Rx Handshake Phase NAK Counter
USB EP0 Rx Handshake Phase STALL Counter
Reserved for future use
Reserved for future use
USB EP2 Data Phase Timeout Counter
USB EP2 Data Phase CRC Error Counter
USB EP2 Data Phase Bitstuff Error Counter
Reserved for future use
Reserved for future use
USB EP3 Data Phase NAK Counter
USB EP3 Data Phase STALL Counter
Reserved for future use
Reserved for future use
USB EP3 Handshake Phase Timeout Counter
Reserved for future use
Reserved for future use
Reserved for future use
USB EP4 Data Phase Timeout Counter
USB EP4 Data Phase CRC Error Counter
USB EP4 Data Phase Bitstuff Error Counter
USB EP4 Data Phase Data Toggle Error Counter
USB EP4 Handshake Phase Timeout Counter
USB EP4 Handshake Phase NAK Counter
USB EP4 Handshake Phase STALL Counter
Reserved for future use
USB EP5 Data Phase NAK Counter
USB EP5 Data Phase STALL Counter
Reserved for future use
Reserved for future use
USB EP5 Handshake Phase Timeout Counter
Reserved for future use
Reserved for future use
Reserved for future use
USB EP6 Data Phase Timeout Counter
USB EP6 Data Phase CRC Error Counter
USB EP6 Data Phase Bitstuff Error Counter
USB EP6 Data Phase Data Toggle Error Counter
USB EP6 Handshake Phase Timeout Counter
USB EP6 Handshake Phase NAK Counter
USB EP6 Handshake Phase STALL Counter
Reserved for future use
Base address
ATM Cell Processor (ATM)
Ethernet Controller (Ether) #1 (n = 1)
Ethernet Controller (Ether) #2 (n = 2)
USB Controller (USB)
System Controller (SYSCNT)
- 1001_0000H
- 1000_2000H
- 1000_3000H
- 1000_1000H
- 1000_0000H