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CHAPTER 2 V
R
4120A
194
Preliminary User’s Manual S14767EJ1V0UM00
Figure 2-73. Common Exception Handling (1/2)
(a) Handling exceptions other than Cold reset, Soft reset, NMI, and TLB/XTLB Refill (hardware)
BD bit
←
1
EPC
←
PC
4
EXL
←
1
Kernel mode is set and interrupts
are disabled.
= 0 (Normal)
= 1 (bootstrap)
Check for multiple exceptions
Kernel mode is set and interrupts
are disabled.
EntryHi and X/Context registers are set only
when a TLB Refill, TLB Invalid, or TLB
Modified exception occurs.
X/Context
←
VPN2
Set Cause register (ExcCode, CE)
Entry Hi
←
VPN2, ASID
To guideline to common exception handler
Start
Yes
EXL = 1
(SR1)
No
No
Yes
Instruction
in branch delay
slot
BEV
PC
←
0xFFFF FFFF BFC0 0200 +180
(Unmapped, uncached space)
M16 = 1
(config20)
PC
←
0xFFFF FFFF 8000 0000 +180
(Unmapped, cacheable space)
No
Instruction
in delay slot
BD bit
←
1
EPC
←
PC
4
PC
2
Note 1
EPC
←
EIM
EPC
←
EIM
BD bit
←
0
EPC
←
PC
PC
2
Note 2
No
Yes
Yes
BD bit
←
0
EPC
←
PC
BadVAddr is set only when a TLB Refill, TLB
Invalid, or TLB Modified exception occurs
(BadVAddr is not set when a Bus Error
exception occurs).
Notes 1.
When the JR or JALR instruction of MIPS16 instructions
When the Extend instruction of MIPS16 instructions
2.
Remark
The interrupts can be masked by setting the IE or IM bit.
The Watch exception can be set to pending state by setting the EXL bit to 1.