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參數(shù)資料
| 型號(hào)： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁(yè)數(shù)： | 95/248頁(yè) |
| 文件大?。?/td> | 1459K |
| 代理商： | T7633 |
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Advance Data Sheet
May 1998
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
85
Lucent Technologies Inc.
Signaling Access
Signaling information can be accessed by three different methods: transparently through the CHI, via the control
registers, or via the CHI associated signaling mode.
Transparent Signaling
This mode is enabled by setting register FRM_PR44 bit 0 to 1.
Data at the received RCHIDATA interface passes through the framer undisturbed. The framer generates an arbi-
trary signaling multiframe in the transmit and receive directions to facilitate the access of signaling information at
the system interface.
DS1: Robbed-Bit Signaling
Microprocessor Control Registers
To enable signaling, register FRM_PR44 bit 0 must be set to 0 (default).
The information written into the F and G bits of the transmit signaling registers, FRM_TSR0—FRM_TSR23, define
the robbed-bit signaling mode for each channel for both the transmit and receive directions. The per-channel pro-
gramming allows the system to combine voice channels with data channels within the same frame.
The receive-channel robbed-bit signaling mode is always defined by the state of the F and G bits in the corre-
sponding transmit signaling registers for that channel. The received signaling data is stored in the receive signaling
registers, FRM_RSR0—FRM_RSR23, while receive framer is in both the frame and superframe alignment states.
Updating the receive signaling registers can be inhibited on-demand, by setting register FRM_PR44 bit 3 to 1, or
automatically when either a framing error event, a loss of frame, or superframe alignment state is detected or a
controlled slip event occurs. The signaling inhibit state is valid for at least 32 frames after any one of the following:
a framing errored event, a loss of frame and/or superframe alignment state, or a controlled slip event.
In the common channel signaling mode, data written in the transmit signaling registers is transmitted in channel 24
of the transmit line bit stream. The F and G bits are ignored in this mode. The received signaling data from channel
24 is stored in receive signaling registers FRM_RSR0—FRM_RSR23 for T1.
Associated Signaling Mode
This mode is enabled by setting register FRM_PR44 bit 2 to 1.
Signaling information in the associated signaling mode (ASM) is allocated an 8-bit system time slot in conjunction
with the pay load data information for a particular channel. The default system data rate in the ASM mode is
4.096 Mbits/s. Each system channel consists of an 8-bit payload time slot followed by its corresponding 8-bit sig-
naling time slot. The format of the signaling byte is identical to that of the signaling registers.
In the ASM mode, writing the transmit signaling registers will corrupt the transmit signaling data. In the transmit sig-
naling register ASM (TSR-ASM) format, enabled by setting register FRM_PR44 bit 2 and bit 5 to 1, the system
must write into the F and G bit
1
of the transmit signaling registers to program the robbed-bit signaling state mode of
each DS0. The ABCD bits are sourced from the RCHI ports when TSR-ASM mode is enabled.
1. All other bits in the signaling registers are ignored, while the F and G bits in the received RCHIDATA stream are ignored.
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