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Advance Data Sheet
May 1998
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
185
Lucent Technologies Inc.
Framer Register Architecture
(continued)
Framer Parameter/Control Registers
(continued)
Alarm Filter Register (FRM_PR10)
The bits in this register enable various control options. The default setting is 00 (hex).
Table 138. Alarm Filter Register (FRM_PR10) (66A; C6A)
Bit 6 and bit 7 of FRM_PR10 control the evaluation of the bursty errored parameter as defined in Table 139 below.
The EST parameter refers to the errored second threshold defined in register FRM_PR11. The SEST parameter
refers to the severely errored second threshold defined in registers FRM_PR12 and FRM_PR13.
Bit
0
Symbol
SSa6M
Description
Synchronous Sa6 Monitoring.
A
0 enables the asynchronous monitoring of the Sa6
codes relative to the receive CRC-4 submultiframe. A 1
enables synchronous monitoring
of the Sa6 pattern relative to the receive CRC-4 submultiframe.
AIS Detection Mode.
A 0 enables the detection of received line AIS as described in
ETSI Draft prETS 300 233:1992. A 1 enables the detection of received line AIS as
described in ITU Rec. G.775.
FER Enable (DS1 Only).
A 0 enables only the detection of F
T
framing bit errors in D4
and SLC-96 modes. A 1 enables the detection of F
T
and F
S
framing bit errors.
Not FAS Framing Bit Error Control (CEPT Only).
A 0 enables the monitoring of
errored FAS and errored NOT FAS frames in the framing bit error counter, registers
FRM_SR10 and FRM_SR11. A 1 enables the monitoring of only errored FAS frames in
this error counter.
CNUCLB Enable (CEPT Only).
A 0 enables payload loopback with regenerated framing
and CRC bits in register FRM_PR24. A 1 enables CEPT nailed-up connect loopback in
register FRM_PR24.
Reserved.
Set to 0.
Receive A-Bit Filter (CEPT Only).
A 0 makes the occurrence of three consecutive
A bit = 1 events assert and three consecutive A bit = 0 events deassert the remote frame
alarm, register FRM_SR2 bit 0. A 1 enables the occurrence of a single A-bit event to
deassert the remote frame alarm.
1
AISM
2
FEREN
NFFE
3
CNUCLBEN
4
5
—
RABF
Table 139. Errored Event Threshold Definition
Bit 7,
FRM_PR10
ESM1
Bit 6,
FRM_PR10
ESM0
Errored Second (ES)
Definition
Bursty Errored
Second (BES)
Definition
Severely Errored
Second (SES)
Definition
0
0
Default values in Table 44, Event Counters Definition, on page 97.
0
1
ES = 1 when:
Errored events > EST
BES = 0
SES = 1 when:
Errored events > SEST
Other Combinations
Reserved.