參數資料
型號: T7633
廠商: Lineage Power
英文描述: Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器)
中文描述: 雙T1/E1的3.3伏短途終結者(雙T1/E1的3.3短通信距離終端器)
文件頁數: 70/248頁
文件大小: 1459K
代理商: T7633
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Advance Data Sheet
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
May 1998
60
Lucent Technologies Inc.
Frame Formats
(continued)
T1 Framing Structures
(continued)
Internal SLC-96 Stack Source.
Optionally, a SLC-96 FDL stack may be used to insert and correspondingly extract
the FDL information in the SLC-96 frame format.
The transmit SLC-96 FDL bits are sourced from the transmit framer SLC-96 FDL stack. The SLC-96 FDL stack
(see FRM_PR31—FRM_PR35) consists of five 8-bit registers that contain the SLC-96 FS and D-bit information as
shown in Table 23. The transmit stack data is transmitted to the line when the stack enable mode is active in the
parameter registers FRM_PR21 bit 6 = 1 and FRM_PR29 bit 5—bit 7 = x10 (binary).
The receive SLC-96 stack data is received when the receive framer is in the superframe alignment state. In the
SLC-96 mode, while in the loss of superframe alignment (LSFA) state, updating of the receive framer SLC-96 stack
is halted and neither the receive stack interrupt nor receive stack flag are asserted.
Table 23. Transmit and Receive SLC-96 Stack Structure
Bit 5—bit 0 of the first 2 bytes of the SLC-96 FDL stack in Table 23 are transmitted to the line as the SLC-96 F
S
sequence. Bit 7 of the third stack register is transmitted as the C
1
bit of the SLC-96 D sequence. The spoiler bits
(SPB1, SPB2, SPB3, and SPB4) are taken directly from the transmit stack. The protocol for accessing the SLC-96
stack information for the transmit and receive framer is described below. The transmit SLC-96 stack must be written
with valid data when transmitting stack data.
The device indicates that it is ready for an update of its transmit stack by setting register FRM_SR4 bit 5 (SLC-96
transmit FDL stack ready) high. At this time, the system has about 9 ms to update the stack. Data written to the
stack during this interval will be transmitted during the next SLC-96 superframe D-bit interval. By reading bit 5 in
register SR4, the system clears this bit so that it can indicate the next time the transmit stack is ready. If the trans-
mit stack is not updated, then the content of the stack is retransmitted to the line. The start of the SLC-96 36-frame
F
S
interval of the transmit framer is a function of the first 2 bytes of the SLC-96 transmit stack registers. These
bytes must be programmed as shown in Table 23. Programming any other state into these two registers disables
the proper transmission of the SLC-96 D bits. Once programmed correctly, the transmit SLC-96 D-bit stack is trans-
mitted synchronous to the transmit SLC-96 superframe structure.
On the receive side, the device indicates that it has received data in the receive FDL stack (registers FRM_SR54—
FRM_SR58) by setting bit 4 in register FRM_SR4 (SLC-96 receive FDL stack ready) high. The system then has
about 9 ms to read the content of the stack before it is updated again (old data lost). By reading bit 4 in register
FRM_SR4, the system clears this bit so that it can indicate the next time the receive stack is ready. As explained
above, the SLC-96 receive stack is not updated when superframe alignment is lost.
Table 22. SLC-96 Line Switch Message Codes
S
1
1
1
1
1
1
0
0
0
S
2
1
1
1
1
0
1
1
0
S
3
1
1
0
0
1
0
0
1
S
4
1
0
1
0
0
1
0
0
Code Definition
Idle
Switch line A receive
Switch line B transmit
Switch line C transmit
Switch line D transmit
Switch line B transmit and receive
Switch line B transmit and receive
Switch line B transmit and receive
Register
Number
1 (LSR)
Bit 7
(MSB)
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
1
0
0
0
0
1
1
2
0
0
0
0
0
1
1
1
3
4
5
C
1
C
9
M
3
C
2
C
10
A
1
C
3
C
11
A
2
C
4
C
5
C
6
C
7
M
1
S
4
C
8
M
2
SPB
1
= 0 SPB
2
= 1 SPB
3
= 0
S
1
S
2
S
3
SPB
4
= 1
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