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Advance Data Sheet
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
May 1998
140
Lucent Technologies Inc.
Microprocessor Interface
Overview
The T7633 device is equipped with a microprocessor interface that can operate with most commercially available
microprocessors. The microprocessor interface provides access to all the internal registers through a 12-bit
address bus and an 8-bit data bus. Inputs MPMODE and MPMUX (pins 74 and 76) are used to configure this inter-
face into one of four possible modes, as shown in Table 65. The MPMUX setting selects either a multiplexed (8-bit
address/data bus, AD[7:0]) or a demultiplexed (12-bit address bus, A[11:0] and an 8-bit data bus AD[7:0]) mode of
operation. The MPMODE setting selects the associated set of control signals required to access a set of registers
within the device.
The microprocessor interface can operate at speeds up to 33 MHz in interrupt-driven or polled mode without requir-
ing any wait-states. For microprocessors operating at greater than 33 MHz, the RDY_DTACK output (pin 100) may
be used to introduce wait-states in the read/write cycles.
In the interrupt-driven mode, one or more device alarms will assert the INTERRUPT output (pin 99) once per alarm
activation. After the microprocessor identifies the source(s) of the alarm(s) (by reading the global interrupt register)
and reads the specific alarm status registers, the INTERRUPT output will deassert. In the polled mode, however,
the microprocessor monitors the various device alarm status by periodically reading the alarm status registers
within the line interface unit, framer, and HDLC blocks without the use of INTERRUPT. In both interrupt and polled
methods of alarm servicing, the status registers within an identified block will clear on a microprocessor read cycle
only when the alarm condition within that block no longer exists; otherwise, the alarm status register bit remains
set.
The powerup default states for the line interface unit, framer, and the HDLC blocks are discussed in their respective
sections. All read/write registers within these blocks must be written by the microprocessor on system start-up to
guarantee proper device functionality.
Register addresses not defined in this data sheet must not be written.
Details concerning the microprocessor interface configuration modes, pinout definitions, clock specifications,
register address map, I/O timing specifications, and the I/O timing diagrams are described in the following sections.
Microprocessor Configuration Modes
Table 65 highlights the four microprocessor modes controlled by the MPMUX and MPMODE inputs (pins 76 and
74).
*
The DTACK signal is asynchronous to the MPCLK signal.
ALE_AS may be connected to ground in this mode.
Table 65. Microprocessor Configuration Modes
Mode
MPMODE
MPMUX
Address/Data Bus
Generic Control, Data, and
Output Pin Names
CS
,
AS
,
DS
, R/
W
, A[11:0], AD[7:0], INT,
DTACK
CS
,
AS
,
DS
, R
/W
, A[11:8], AD[7:0], INT,
DTACK
CS
,
ALE
,
RD
,
WR
, A[11:0], AD[7:0], INT, RDY
CS
,
ALE
,
RD
,
WR
, A[11:8], AD[7:0], INT, RDY
Mode 1
Mode 2
Mode 3
Mode 4
0
0
1
1
0
1
0
1
DEMUXed*
MUXed
DEMUXed*
MUXed