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參數(shù)資料
| 型號： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁數(shù)： | 128/248頁 |
| 文件大?。?/td> | 1459K |
| 代理商： | T7633 |
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Advance Data Sheet
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
May 1998
118
Lucent Technologies Inc.
Facility Data Link (FDL)
(continued)
HDLC Operation
(continued)
Using the Transmitter Status and Fill Level
The transmitter-interrupt level bits, register FDL_PR3 bit 0—bit 5, allow the user to instruct the FDL HDLC block to
interrupt the host processor whenever the transmitter has a predetermined number of empty locations. The number
of locations selected determines the time between transmitter empty, register FRM_SR0 bit 1 (FTEM), interrupts.
The transmitter status bits, register FDL_SR1, report the number of empty locations in the FDL transmitter FIFO.
The transmitter empty dynamic bit, register FDL_SR1 bit 7 (FTED), like the FTEM interrupt bit, is set to 1 when the
number of empty locations is less than or equal to the programmed empty level. FTED returns to 0 when the
transmitter is filled to above the programmed empty level. Polled interrupt systems can use FTED to determine
when they can write to the FDL transmit FIFO.
Transparent Mode
The FDL HDLC block can be programmed to operate in the transparent mode by setting register FDL_PR9 bit 6
(FTRANS) to 1. In the transparent mode of operation, no HDLC processing is performed on user data. The
transparent mode can be exited at any time by setting FDL_PR9 bit 6 (FTRANS) to 0. It is recommended that the
transmitter be disabled when changing in and out of transparent mode. The transmitter should be reset by setting
FDL_PR1 bit 5 (FTR) to 1 whenever the mode is changed.
In the transmit direction, the FDL HDLC takes data from the transmit FIFO and transmits that data exactly bit-for-bit
on the TFDL interface. Transmit data is octet-aligned to the first TFDLCK after the transmitter has been enabled.
The bits are transmitted least significant bit first. When there is no data in the transmit FIFO, the FDL HDLC either
transmits all 1s, or transmits the programmed HDLC transmitter idle character (register FDL_PR5) if register
FDL_PR9 bit 6 (FMATCH) is set to 1. To cause the transmit idle character to be sent first, the character must be
programmed before the transmitter is enabled.
The transmitter empty interrupt, register FDL_SR0 bit 1 (FTEM), acts as in the HDLC mode. The transmitter-done
interrupt, register FDL_SR0 bit 0 (FTDONE), is used to report an empty FDL transmit FIFO. The FTDONE interrupt
thus provides a way to determine transmission end. Register FDL_SR0 bit 2 (FTUNDABT) interrupt is not active in
the transparent mode.
In the receive direction, the FDL HDLC block loads received data from the RFDL interface directly into the receive
FIFO bit-for-bit. The data is assumed to be least significant bit first. If FMATCH register FDL_PR9 bit 6 is 0, the
receiver begins loading data into the receive FIFO beginning with the first RFDLCK detected after the receiver has
been enabled. If the FMATCH bit is set to 1, the receiver does not begin loading data into the FIFO until the
receiver match character has been detected. The search for the receiver match character is in a sliding window
fashion if register FDL_PR9 bit 4 (FALOCT) bit is 0 (align to octet), or only on octet boundaries if FALOCT is set to
1. The octet boundary is aligned relative to the first RFDLCK after the receiver has been enabled. The matched
character and all subsequent bytes are placed in the receive FIFO. An FDL receiver reset, register FDL_PR1 bit 4
(FRR) = 1, causes the receiver to realign to the match character if FMATCH is set to 1.
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