參數(shù)資料
型號: T7633
廠商: Lineage Power
英文描述: Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器)
中文描述: 雙T1/E1的3.3伏短途終結(jié)者(雙T1/E1的3.3短通信距離終端器)
文件頁數(shù): 45/248頁
文件大?。?/td> 1459K
代理商: T7633
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Advance Data Sheet
May 1998
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
35
Lucent Technologies Inc.
Line Interface Unit: Transmit
(continued)
LIU Transmitter Configuration Modes
LIU Transmitter Zero Substitution Encoding (CODE)
LIU transmitter zero substitution (B8ZS/HDB3) encoding can be activated only in the single-rail (DUAL = 0) system/
framer interface mode. It is activated by setting CODE = 1 (register LIU_REG3, bit 2). Data transmitted from the
framer interface on TPD-LIU will be B8ZS/HDB3 encoded before appearing on TTIP and TRING at the line inter-
face.
LIU Transmitter Alarm Indication Signal Generator (XLAIS)
When the transmit alarm indication signal control is set (XLAIS = 1) for a given channel (see register LIU_REG5,
bit 1), a continuous stream of bipolar 1s is transmitted to the line interface. The internal LIU to framer TPD interface
(TPD) and internal LIU to framer TND interface (TND) signals are ignored during this mode. The XLAIS control is
ignored when a remote loopback (RLOOP) is selected using loopback control bits LOOPA and LOOPB (register
LIU_REG5, bits 2 to 3). The clock source used for the alarm indication signal is TLCK if present or INTSYSCK if
TLCK is not present. The clock tolerance must meet the nominal transmission specifications of 1.544 MHz
±
32 ppm for DS1 (T1), or 2.048 MHz
±
50 ppm CEPT (E1).
The XLAIS bit is defaulted to 1 on hardware reset allowing the transmitter to send AIS as soon as clocks are avail-
able, without needing to write the LIU registers
1
. Because the transmit equalization bits are needed to determine
the correct system rate (DS1/E1), the reset default state of the equalization bits EQ2, EQ1, EQ0 (register
LIU_REG6, bits 0—2) can be predetermined by setting the DS1_CEPT pin (see Table 6 on page 34). The default
transmit equalization is EQ2, EQ1, and EQ0 = 000 (0 dB T1/DS1) when DS1_CEPT = 1, and EQ2, EQ1, and EQ0
= 110 (CEPT 120
/75
) when DS1_CEPT = 0. The transmit equalization bits can be subsequently programmed
to any state by writing the LIU register regardless of the state of the DS1_CEPT pin. The DS1_CEPT pin is only
used to determine the reset default state of the equalization bits.
1. If TLCK from the framer is present, automatic transmission of AIS upon reset will occur only if the CHI common control register FRM_PR45
bit 0 = 0, the default, or low-frequency PLLCK mode. In this case, PLLCK will be equal to the line transmit rate, either 1.544 MHz for DS1 or
2.048 MHz for CEPT.
LIU Transmitter Alarms
Loss of LIU Transmit Clock (LOTC) Alarm
A loss of LIU transmit clock alarm (LOTC = 1, see register LIU_REG0, bit 3) is indicated if any of the clocks used in
the LIU transmitter pathes are absent. This includes loss of TLCK-LIU input, loss of RLCK-LIU during remote loop-
back, loss of jitter attenuator output clock (when enabled in transmit path), or the internal loss of clock from the
pulse-width controller. For all of these conditions, the LIU transmitter timing clock is lost and no data can be driven
onto the line. Output drivers TTIP and TRING are placed in a high-impedance state when this alarm is active. The
LOTC alarm asserts between 3
μ
s and 16
μ
s after the clock is lost, and deasserts immediately after detecting the
first clock edge. The LOTC alarm status bit will latch the alarm and remain set until being cleared by a read (clear
on read). Upon the transition from LOTC = 0 to LOTC = 1, an interrupt will be generated if the LOTC interrupt
enable bit LOTCIE (register LIU_REG1, bit 3) is set. The reset default is LOTCIE = 0.
An LOTC alarm may occur when RLOOP is activated and deactivated due to the phase transient that occurs as
TLCK-LIU switches its source to and from RLCK-LIU. Setting the RLOOP alarm prevention PRLALM = 1 (register
LIU_REG4, bit 3) prevents the LOTC alarm from occurring at the activation and deactivation of RLOOP but allows
the alarm to operate normally during the RLOOP active period. The reset default is PRLALM = 0.
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