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參數(shù)資料
| 型號： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁數(shù)： | 26/248頁 |
| 文件大?。?/td> | 1459K |
| 代理商： | T7633 |
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Advance Data Sheet
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
May 1998
16
Lucent Technologies Inc.
Functional Description
(continued)
The Lucent T7633 Dual T1/E1 Terminator provides two complete T1/E1 interfaces each consisting of a fully inte-
grated, full-featured, short-haul line interface transceiver and a full-featured primary rate framer with an HDLC for-
matter for facility data link access. The T7633 provides glueless interconnection from a T1 or E1 analog line
interface to devices interfacing to its concentration highway interface (CHI); for example, the T7270 Time Slot Inter-
changer or T7115A Synchronous Protocol Data Formatter.
The line interface receiver performs clock and data recovery using a digital phase-locked loop, thereby avoiding
false lock conditions that are common when recovering sparse data patterns with an analog implementation. The
receiver’s equalization circuit guarantees a high level of interference immunity. The receive line unit monitors the
amplitude at the receive input for analog loss of signal detection and the pulse density of the receive signal for dig-
ital loss of signal detection. The receive line unit may be programmed to detect bipolar violations. The line interface
unit may be optionally bypassed.
The line interface unit’s transmit equalization is done with low-impedance output drivers that provide shaped wave-
forms to the transformer, guaranteeing template conformance. The transmitter will interface to the digital cross con-
nect (DSX) at lengths up to 655 feet for DS1 operation, and line impedances of 75
or 120
for CEPT-E1
operation. The transmit line unit monitors nonfunctional links due to faults at the primary of the transmit transformer
and periods of no data transmission.
The line codes supported in the framer unit include AMI, T1 B8ZS, per-channel T1 zero code suppression and ITU-
CEPT HDB3.
The T7633 supports T1 D4, T1DM, and SLC-96 superframes; extended superframe (ESF); ITU-CEPT-E1 basic
frame; ITU-CEPT-E1 time slot 0 multiframe; and time slot 16 multiframe formats.
The receive framer monitors the following alarms: loss of receive clock, loss of frame, alarm indication signal (AIS),
remote frame alarms, and remote multiframe alarms. These alarms are detected as defined by the appropriate
ANSI, AT&T, and ITU standards.
Performance monitoring as specified by AT&T, ANSI, and ITU is provided through counters monitoring bipolar vio-
lation, frame bit errors, CRC errors, CEPT E bit = 0 conditions, CEPT Sa6 codes, errored events, errored seconds,
bursty errored seconds, severely errored seconds, and unavailable seconds.
In-band loopback activation and deactivation codes can be transmitted to the line via the payload or the facility data
link. In-band loopback activation and deactivation codes in the payload or the facility data link are detected.
System, payload, and line loopbacks are programmable.
The default system interface is a 2.048 Mbits/s data and 2.048 MHz clock concentration highway interface (CHI)
serial bus. This CHI interface consists of independent transmit and receive paths. The CHI interface can be recon-
figured into several modes: a 2.048 Mbits/s data interface and 4.096 MHz clock interface, a 4.096 Mbits/s data
interface and 4.096 MHz clock interface, a 4.096 Mbits/s data interface and 8.192 MHz clock interface, a
8.192 Mbits/s data interface and 8.192 MHz clock interface, and 8.192 Mbits/s data interface and 16.384 MHz clock
interface.
The signaling formats supported are T1 per-channel robbed-bit signaling (RBS), channel-24 message-oriented sig-
naling (MOS), ITU-CEPT-E1 channel-associated signaling (CAS), common channel signaling (CCS) (Lucent
T7230A mode), and international remote switching module (IRMS). In the T1, RBS mode voice and data channels
are programmable. The entire payload can be programmed into a data-only (no signaling channels) mode, i.e.,
transparent mode. Signaling access can be through the on-chip signaling registers or the system CHI port in the
associated signaling mode. Data and its associated signaling information can be accessed through the CHI in
either DS1 or CEPT-E1 modes.
Extraction and insertion of the facility data link in ESF, T1DM, SLC-96, or CEPT-E1 modes are provided through a
four-port serial interface or through a microprocessor-accessed, 64-byte FIFO either with HDLC formatting or
transparently. In the T7633’s SLC-96 or CEPT-E1 frame formats, a facility data link (FDL) is provided for FDL
access. The bit-oriented ESF data-link messages defined in ANSI T1.403-1995 are monitored by the receive
framer’s facility data link unit and are transmitted by the transmit framer FDL
The receive framer includes a two-frame elastic store buffer for jitter attenuations that performs control slips and
provides indication of slip directions.
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