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Advance Data Sheet
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
May 1998
182
Lucent Technologies Inc.
Framer Register Architecture
(continued)
Framer Parameter/Control Registers
(continued)
Secondary Interrupt Enable Registers (FRM_PR1—FRM_PR7)
A bit set to 1 in registers FRM_PR1—FRM_PR7 enables the generation of interrupts whenever the corresponding
bit in registers FRM_SR1—FRM_SR7 is set. The default value of these registers is 00 (hex).
Table 128. Interrupt Enable Register (FRM_PR1) (661; C61)
Table 129. Interrupt Enable Register (FRM_PR2) (662; C62)
Table 130. Interrupt Enable Register (FRM_PR3) (663; C63)
Table 131. Interrupt Enable Register (FRM_PR4) (664; C64)
Table 132. Interrupt Enable Register (FRM_PR5) (665; C65)
Table 133. Interrupt Enable Register (FRM_PR6) (666; C66)
Table 134. Interrupt Enable Register (FRM_PR7) (667; C67)
Bit
0—7
Symbol
SR1B0IE—
SR1B7IE
Description
Status Register 1 Interrupt Enable.
A 1 enables events monitored in register FRM_SR1
to generate interrupts. Each bit position in this enable register corresponds to the same
bit position in the status register.
Bit
0—7
Symbol
SR2B0IE—
SR2B7IE
Description
Status Register 2 Interrupt Enable.
A 1 enables events monitored in register FRM_SR2
to generate interrupts. Each bit position in this enable register corresponds to the same
bit position in the status register.
Bit
0—7
Symbol
SR3B0IE—
SR3B7IE
Description
Status Register 3 Interrupt Enable.
A 1 enables events monitored in register FRM_SR3
to generate interrupts. Each bit position in this enable register corresponds to the same
bit position in the status register.
Bit
0—7
Symbol
SR4B0IE—
SR4B7IE
Description
Status Register 4 Interrupt Enable.
A 1 enables events monitored in register FRM_SR4
to generate interrupts. Each bit position in this enable register corresponds to the same
bit position in the status register.
Bit
0—7
Symbol
SR5B0IE—
SR5B7IE
Description
Status Register 5 Interrupt Enable.
A 1 enables events monitored in register FRM_SR5
to generate interrupts. Each bit position in this enable register corresponds to the same
bit position in the status register.
Bit
0—7
Symbol
SR6B0IE—
SR6B7IE
Description
Status Register 6 Interrupt Enable.
A 1 enables events monitored in register FRM_SR6
to generate interrupts. Each bit position in this enable register corresponds to the same
bit position in the status register.
Bit
0—7
Symbol
SR7B0IE—
SR7B7IE
Description
Status Register 7 Interrupt Enable.
A 1 enables events monitored in register FRM_SR7
to generate interrupts. Each bit position in this enable register corresponds to the same
bit position in the status register.