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Advance Data Sheet
May 1998
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
157
Lucent Technologies Inc.
Global Register Structure
(continued)
Global Control Register (GREG4)
This register enables LIU1 to LIU2 loopbacks (bit 2 and bit 3), interrupt 3-state control (bit 4), source of the output
second pulse (bit 5), and interrupt polarity (bit 6).
Table 78. Global Control Register (GREG4) (004)
Device ID and Version Registers (GREG5
—
GREG7)
These bits define the device and version number.
Table 79. Device ID and Version Registers (GREG5
—
GREG7) (005—007)
Bit
0
1
2
Symbol
—
—
T2-R1
Description
Reserved.
Write to zero.
Reserved.
Write to zero.
TLCK2, TPD2, and TND2 to RLCK1, RPD1, and RND1 Connection.
A 1 makes the indi-
cated loopback.
TLCK1, TPD1, and TND1 to RLCK2, RPD2, and RND2 Connection.
A 1 makes the indi-
cated loopback.
INTERRUPT 3-State Control.
This bit along with bit 6 in this register (ALIE) allows the
interrupt pin to be programmed for active-high, active-low, wire OR, or wire AND operation,
as described below:
Bits
Description
4 6
0 0
Programs the interrupt pin to be active-high (1 state) when there is an interrupt
condition and to be inactive (0 state) when there is no interrupt condition.
0 1
Programs the interrupt pin to be active-low (0 state) when there is an interrupt
condition and to be inactive (1 state) when there is no interrupt condition.
1 0
Programs the interrupt pin to be active-high (1 state) when there is an interrupt
condition and to be in the high-impedance state (3-state) when there is no inter-
rupt condition. This allows the interrupt to be wire OR’d with other interrupt pins
on the system board. A pull-down resister is needed on the system board.
1 1
Programs the interrupt pin to be active-low (0 state) when there is an interrupt
condition and to be in the high-impedance state (3-state) when there is no inter-
rupt condition. This allows the interrupt to be wire AND’d with other interrupt
pins on the system board. A pull-up resister is needed on the system board.
SECOND Pulse Source Control.
A 0 enables framer 1 to source the output second pulse
(SECOND). A 1 enables framer 2 to source the output second pulse.
Active-Low Interrupt Enable.
A 1 enables active-low interrupt.
Reserved.
Write to zero.
3
T1-R2
4
ITC
5
SECCTRL
6
7
ALIE
—
Register
GREG5
GREG6
GREG7
Bit 7
0
0
0
Bit 6
1
0
0
Bit 5
1
1
0
Bit 4
1
1
0
Bit 3
0
0
0
Bit 2
1
0
0
Bit 1
1
1
0
Bit 0
0
1
1
Device Code
Device Code
Version #