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Advance Data Sheet
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
May 1998
10
Lucent Technologies Inc.
List of Tables
(continued)
Table
Page
Table 101. CRC-4 Errors at NT1 from NT2 Counter Registers (FRM_SR16—FRM_SR17)
((610—611); (C10—C11))................................................................................................................ 174
Table 102. E Bit at NT1 from NT2 Counter (FRM_SR18—FRM_SR19) ((612—613); (C12—C13)) ................... 174
Table 103. ET Errored Seconds Counter (FRM_SR20—FRM_SR21) ((614—615); (C14—C15))...................... 175
Table 104. ET Bursty Errored Seconds Counter (FRM_SR22—FRM_SR23) ((616—617); (C16—C17))........... 175
Table 105. ET Severely Errored Seconds Counter (FRM_SR24—FRM_SR25) ((618—619); (C18—C19))....... 175
Table 106. ET Unavailable Seconds Counter (FRM_SR26—FRM_SR27) ((61A—61B); (C1A—C1B)).............. 175
Table 107. ET-RE Errored Seconds Counter (FRM_SR28—FRM_SR29) ((61C—61D); (C1C—C1D)).............. 175
Table 108. ET-RE Bursty Errored Seconds Counter (FRM_SR30—FRM_SR31) ((61E—61F); (C1E—C1F)).... 175
Table 109. ET-RE Severely Errored Seconds Counter (FRM_SR32—FRM_SR33)
((620—621); (C20—C21)).................................................................................................................. 175
Table 110. ET-RE Unavailable Seconds Counter (FRM_SR34—FRM_SR35) ((622—623); (C22—C23))......... 176
Table 111. NT1 Errored Seconds Counter (FRM_SR36—FRM_SR37) ((624—625); (C24—C25)).................... 176
Table 112. NT1 Bursty Errored Seconds Counter (FRM_SR38—FRM_SR39) ((626—627); (C26—C27))......... 176
Table 113. NT1 Severely Errored Seconds Counter (FRM_SR40—FRM_SR41) ((628—629); (C28—C29))..... 176
Table 114. NT1 Unavailable Seconds Counter (FRM_SR42—FRM_SR43) ((62A—62B); (C2A—C2B))............ 176
Table 115. NT1-RE Errored Seconds Counter (FRM_SR44—FRM_SR45) ((62C—62D); (C2C—C2D)) ........... 176
Table 116. NT1-RE Bursty Errored Seconds Counter (FRM_SR46—FRM_SR47)
((62E—62F); (C2E—C2F))................................................................................................................. 177
Table 117. NT1-RE Severely Errored Seconds Counter (FRM_SR48—FRM_SR49)
((630—631); (C30—C31)).................................................................................................................. 177
Table 118. NT1-RE Unavailable Seconds Counter (FRM_SR50—FRM_SR51) ((632—633); (C32—C33))....... 177
Table 119. Receive NOT-FAS TS0 Register (FRM_SR52) (634; C34)................................................................ 177
Table 120. Receive Sa Register (FRM_SR53) (635; C35)................................................................................... 177
Table 121.
SLC
-96 FDL Receive Stack (FRM_SR54—FRM_SR63) ((636—63F); (C36—C3F))........................ 178
Table 122. CEPT Sa Receive Stack (FRM_SR54—FRM_SR63) ((636—63F); (C36—C3F))............................. 178
Table 123. Transmit Framer ANSI Performance Report Message Status Register Structure ............................. 179
Table 124. Received Signaling Registers: DS1 Format (FRM_RSR0—FRM_RSR23)
((640—658); (C40—C58)).................................................................................................................. 179
Table 125. Receive Signaling Registers: CEPT Format (FRM_RSR0—FRM_RSR31)
((640—65F); (C40—C5F)).................................................................................................................. 179
Table 126. Summary of Interrupt Group Enable Registers (FRM_PR0—FRM_PR7)
((660—667); (C60—C67)).................................................................................................................. 180
Table 127. Primary Interrupt Group Enable Register (FRM_PR0) (660; C60)..................................................... 181
Table 128. Interrupt Enable Register (FRM_PR1) (661; C61) ............................................................................. 182
Table 129. Interrupt Enable Register (FRM_PR2) (662; C62) ............................................................................. 182
Table 130. Interrupt Enable Register (FRM_PR3) (663; C63) ............................................................................. 182
Table 131. Interrupt Enable Register (FRM_PR4) (664; C64) ............................................................................. 182
Table 132. Interrupt Enable Register (FRM_PR5) (665; C65) ............................................................................. 182
Table 133. Interrupt Enable Register (FRM_PR6) (666; C66) ............................................................................. 182
Table 134. Interrupt Enable Register (FRM_PR7) (667; C67) ............................................................................. 182
Table 135. Framer Mode Bits Decoding (FRM_PR8) (668; C68)......................................................................... 183
Table 136. Line Code Option Bits Decoding (FRM_PR8) (668; C68).................................................................. 183
Table 137. CRC Option Bits Decoding (FRM_PR9) (669, C69)........................................................................... 184
Table 138. Alarm Filter Register (FRM_PR10) (66A; C6A).................................................................................. 185
Table 139. Errored Event Threshold Definition .................................................................................................... 185
Table 140. Errored Second Threshold Register (FRM_PR11) (66B; C6B).......................................................... 186
Table 141. Severely Errored Second Threshold Registers (FRM_PR12—FRM_PR13)
((66C—66D; C6C—C6D))................................................................................................................. 186
Table 142. ET1 Errored Event Enable Register (FRM_PR14) (66E; C6E).......................................................... 186
Table 143. ET1 Remote End Errored Event Enable Register (FRM_PR15) (66F; C6F)...................................... 187
Table 144. NT1 Errored Event Enable Register (FRM_PR16) (670; C70)........................................................... 187