參數(shù)資料
型號(hào)： T7633
廠商： Lineage Power
英文描述： Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器)
中文描述： 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器）
文件頁(yè)數(shù)： 103/248頁(yè)
文件大?。?/td> 1459K
代理商： T7633
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Advance Data Sheet
May 1998
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
93
Lucent Technologies Inc.
Alarms and Performance Monitoring
(continued)
Alarm Definition
(continued)
4. The
SLIP
condition (FRM_SR3 bit 6 and bit 7).
SLIP is defined as the state in which the receive elastic store buffer’s write address pointer from the receive
framer and the read address pointer from the transmit concentration highway interface are equal
1
.
A.
The negative slip (Slip-N) alarm indicates that the receive line clock (RLCK) - transmit CHI clock (TCHICK)
monitoring circuit detects a state of overflow caused by RLCK and TCHICK being out of phase-lock and
the period of the received frame being less than that of the system frame. One system frame is deleted.
The positive slip (Slip-P) alarm indicates the line clock (RLCK) - transmit CHI clock (TCHICK) monitoring
circuit detects a state of underflow caused by RLCK and TCHICK being out of phase-lock and the period of
the received frame being greater than that of the system frame. One system frame is repeated.
5. The
loss of framer receive clock
(LOFRMRLCK, pins 2 and 38).
In the framer mode, FRAMER = 0 (pin 41/141), LOFRMRLCK alarm is asserted high when an interval of
250
μ
s has expired with no transition of RLCK (pin 135/47) detected. The alarm is disabled on the first transi-
tion of RLCK. In the terminator mode, FRAMER = 1 (pin 41/141), LOFRMRLCK is asserted high when SYSCK
(pin 3/35) does not toggle for 250
μ
s. The alarm is disabled on the first transition of SYSCK.
6. The
loss of PLL clock
(LOPLLCK, pins 39 and 143).
LOPLLCK alarm is asserted high when an interval of 250
μ
s has expired with no transition of PLLCK detected.
The alarm is disabled 250
μ
s after the first transition of PLLCK. Timing for LOPLLCK is shown in Figure 38.
B.
1. After a reset, the read and write pointers of the receive path elastic store will be set to a known state.
5-6564(F)r.2
Figure 38. Timing for Generation of LOPLLCK (Pin 39/143)
Table 40. Alarm Indication Signal Conditions
Framing Format
Remote Frame Alarm Format
T1
Loss of frame alignment occurs and the incoming signal has two (2) or fewer zeros in
each of two consecutive double frame periods (386 bits).
As described in Draft prETS 300 233:1992 Section 8.2.2.4, loss of frame alignment
occurs and the framer receives a 512 bit period containing two or less binary zeros. This
is enabled by setting register FRM_PR10 bit 1 to 0.
As described in ITU Rec. G.775, the incoming signal has two or fewer zeros in each of
two consecutive double frame periods (512 bits). AIS is cleared if each of two consecutive
double frame periods contains three or more zeros or frame alignment signal (FAS) has
been found. This is enabled by setting register FRM_PR10 bit 1 to 1.
CEPT ETSI
CEPT ITU
PLLCK
LOPLLCK
RCHICK
250
μ
s
250
μ
s
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