參數(shù)資料
型號(hào): T7689
廠商: Lineage Power
英文描述: 5.0 V T1 Quad Line Interface(5.0 V T1四線接口)
中文描述: 5.0V的T1四線接口(5.0V的T1四線接口)
文件頁(yè)數(shù): 1/38頁(yè)
文件大小: 548K
代理商: T7689
Data Sheet
May 1998
T7689 5.0 V T1 Quad Line Interface
Features
I
Four fully integrated T1 line interfaces
I
Includes all driver, receiver, equalization, clock
recovery, and jitter attenuation functions
I
Ultralow power consumption
I
Robust operation for increased system margin
I
High interference immunity
I
On-chip transmit equalization for improved
sensitivity
I
Low-impedance drivers for reduced power
consumption
I
Selectable transmit or receive, jitter attenuation/
clock smoothing
I
3-state transmit drivers
I
High-speed, microprocessor interface
I
Automatic transmit monitor function
I
Per-channel powerdown
I
For use in systems that are compliant with AT&T
CB119; TR-TSY-000170, TR-TSY-000009, TR-
TSY-000499, TR-TSY-000253; ANSI T1.102 and
T1.403
I
Common transformer for transmit/receive
I
Fine-pitch (25 mil spacing) surface-mount
package, 100-pin bumpered quad flat pack
I
–40
°
C to +85
°
C operating temperature range
Applications
I
SONET/SDH multiplexers
I
Asynchronous multiplexers (M13)
I
Digital access cross connects (DACs)
I
Channel banks
I
Digital radio base stations, remote wireless
modules
I
PBX interfaces
Description
The T7689 is a fully integrated quad line interface
containing four transmit and receive channels for use
in North American (T1/DS1) applications. The device
has many of the same functions as the Lucent Tech-
nologies Microelectronics Group T7290A and pro-
vides additional flexibility for the system designer.
Included is a parallel microprocessor interface that
allows the user to define the architecture, initiate
loopbacks, and monitor alarms. The interface is com-
patible with many commercially available micropro-
cessors.
The receiver performs clock and data recovery using
a fully integrated digital phase-locked loop. This digi-
tal implementation prevents false-lock conditions that
are common when recovering sparse data patterns
with analog phase-locked loops. Equalization cir-
cuitry in the receiver guarantees a high level of inter-
ference immunity. As an option, the raw sliced data
(no retiming) can be output on the receive data pins.
Transmit equalization is implemented with low-
impedance output drivers that provide shaped wave-
forms to the transformer, guaranteeing template con-
formance. The quad device will interface to the digital
cross connect (DSX) at lengths of up to 655 ft. for
DS1 operation.
A selectable jitter attenuator may be placed in the
receive signal path for low-bandwidth line-
synchronous applications, or it may be placed in the
transmit path for multiplexer applications where DS1
signals are demultiplexed from higher rate signals.
The jitter attenuator will perform the clock smoothing
required on the resulting demultiplexed gapped
clock.
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