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參數(shù)資料
| 型號： | T7689 |
| 廠商： | Lineage Power |
| 英文描述： | 5.0 V T1 Quad Line Interface(5.0 V T1四線接口) |
| 中文描述： | 5.0V的T1四線接口（5.0V的T1四線接口） |
| 文件頁數(shù)： | 31/38頁 |
| 文件大?。?/td> | 548K |
| 代理商： | T7689 |
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Data Sheet
May 1998
T7689 5.0 V T1 Quad Line Interface
31
Lucent Technologies Inc.
XCLK Reference Clock
The device requires a high-frequency reference clock for both clock/data recovery and jitter attenuation options
(CDR = 1, JAR = 1, or JAT = 1). The XCLK signal (pin 29) is conditionally required if the MPCLK signal (pin 83) is
not supplied for interrupt generation in the microprocessor interface. For any other device configuration, XCLK is
not required. If it is required, XCLK must be a continuously active (i.e., ungapped, unjittered, and unswitched) and
an independent reference clock, such as an external system oscillator or system clock, for proper operation. It must
not be derived from any recovered line clock (i.e., from RCLK or any synthesized frequency of RCLK). The specifi-
cations for XCLK are defined in Table 20.
Power Supply Bypassing
External bypassing is required for all channels. A 1.0
μ
F capacitor must be connected between V
DD
X and GNDX.
In addition, a 0.1
μ
F capacitor must be connected between V
DDD
and GND
D
, and a 0.1
μ
F capacitor must be con-
nected between V
DDA
and GND
A
. Ground plane connections are required for GNDX, GND
D
, and GND
A
. Power
plane connections are also required for V
DD
X and V
DDD
. The need to reduce high-frequency coupling into the ana-
log supply (V
DDA
) may require an inductive bead to be inserted between the power plane and the V
DDA
pin of every
channel.
External bypassing is also required for the microprocessor power supply pins. A 0.1
μ
F capacitor must be con-
nected between every pair of V
DDC
and GND
C
pins. V
DDC
and GND
C
are connected directly to the power and
ground planes, respectively.
Capacitors used for power supply bypassing should be placed as close as possible to the device pins for maximum
effectiveness.
Table 20. XCLK Timing Specifications
Parameter
Value
Unit
Min
Typ
Max
Frequency:
DS1
Range
Duty Cycle
—
24.704
—
—
—
100
60
MHz
ppm
%
–100
40
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