參數(shù)資料
型號： T7689
廠商： Lineage Power
英文描述： 5.0 V T1 Quad Line Interface(5.0 V T1四線接口)
中文描述： 5.0V的T1四線接口（5.0V的T1四線接口）
文件頁數(shù)： 7/38頁
文件大?。?/td> 548K
代理商： T7689
Data Sheet
May 1998
T7689 5.0 V T1 Quad Line Interface
7
Lucent Technologies Inc.
17
TPD1/
TDATA1
I
Transmit Positive Data.
When in dual-rail mode (DUAL = 1: register 5,
bit 4), this signal is the transmit positive NRZ input data from the terminal
equipment.
Transmit Data.
When in single-rail mode (DUAL = 0: register 5, bit 4), this
signal is the transmit NRZ input data from the terminal equipment.
35
TPD2/
TDATA2
67
TPD3/
TDATA3
85
TPD4/
TDATA4
18
TCLK1
I
Transmit Clock.
DS1 (1.544 MHz
±
32 ppm). Clock signal from the terminal
equipment.
34
TCLK2
68
TCLK3
84
TCLK4
19
WR_DS
I
Write (Active-Low)
. If MPMODE = 1 (pin 21), this pin is asserted low by the
microprocessor to initiate a write cycle.
Data Strobe (Active-Low)
. If MPMODE = 0 (pin 21), this pin becomes the
data strobe for the microprocessor. When R/W = 0 (write), a low applied to
this pin latches the signal on the data bus into internal registers.
20
MPMUX
I
Microprocessor Multiplex Mode
.
Setting MPMUX = 1 allows the micropro-
cessor interface to accept multiplexed address and data signals. Setting
MPMUX = 0 allows the microprocessor interface to accept demultiplexed
(separate) address and data signals.
21
MPMODE
I
Microprocessor Mode
.
When MPMODE = 1, the device uses the address
latch enable type microprocessor read/write protocol with separate read and
write controls. Setting MPMODE = 0 allows the device to use the address
strobe type microprocessor read/write protocol with a separate data strobe
and a combined read/write control.
22
RD_R/W
I
Read (Active-Low)
. If MPMOD = 1 (pin 21), this pin is asserted low by the
microprocessor to initiate a read cycle.
Read/Write
. If MPMODE = 0 (pin 21), this pin is asserted high by the micro-
processor to indicate a read cycle or asserted low to indicate a write cycle.
23
ALE_AS
I
Address Latch Enable
. If MPMODE = 1 (pin 21), this pin becomes the
address latch enable for the microprocessor. When this pin transitions from
high to low, the address bus inputs are latched into the internal registers.
Address Strobe (Active-Low)
. If MPMODE = 0 (pin 21), this pin becomes
the address strobe for the microprocessor. When this pin transitions from
high to low, the address bus inputs are latched into the internal registers.
24
CS
I
u
Chip Select (Active-Low)
. This pin is asserted low by the microprocessor
to enable the microprocessor interface. If MPMUX = 1 (pin 20),
CS
can be
externally tied low to use the internal chip selection function (see the Inter-
nal Chip Select Function section). An internal 100 k
pull-up is on this pin.
Table 1. Pin Descriptions
(continued)
Pin
Symbol
Type
*
Name/Description
* P = power, I = input, O = output, and I
u
= input with internal pull-up.
Pin Information
(continued)
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