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參數(shù)資料
| 型號： | T7689 |
| 廠商： | Lineage Power |
| 英文描述： | 5.0 V T1 Quad Line Interface(5.0 V T1四線接口) |
| 中文描述： | 5.0V的T1四線接口（5.0V的T1四線接口） |
| 文件頁數(shù)： | 12/38頁 |
| 文件大小： | 548K |
| 代理商： | T7689 |
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Data Sheet
May 1998
T7689 5.0 V T1 Quad Line Interface
12
Lucent Technologies Inc.
Receiver
(continued)
DS1 Receiver Specifications
During DS1 operation, the receiver will perform as specified in Table 4.
* Below the nominal pulse amplitude of 3.0 V using external line interface circuitry described in Figure 12 and Table 21.
Amount of cable loss.
Using external line interface circuitry described in Figure 12 and Table 21.
Table 4. DS1 Receiver Specifications
Parameter
Min
Typ
Max
Unit
Specification
Analog Loss of Signal:
Threshold
Hysteresis
Maximum Sensitivity
Jitter Transfer:
3 dB Bandwidth
Peaking
Generated Jitter
20
—
11
17
4
15
—
—
—
dB*
dB
dB
—
—
—
—
—
—
3.84
—
0.032
—
0.1
0.04
kHz
dB
UI
pk-pk
TR-TSY-000499
TR-TSY-000499,
ITU-T G.824
ITU-T G.823-4,
TR-TSY-000009,
TR-TSY-000499,
TR-TSY-000170
Jitter Tolerance
—
—
—
—
Return Loss
:
51 kHz to 102 kHz
102 kHz to 1.544 MHz
1.544 MHz to 2.316 MHz
Digital Loss of Signal:
Flag Asserted, Consecutive Bit
Positions
Flag Deasserted
Data Density
Maximum Consecutive
Zeros
14
20
16
—
—
—
—
—
—
dB
dB
dB
—
—
—
100
12.5
—
—
—
—
—
—
—
—
15
99
zeros
% ones
zeros
zeros
—
—
TR-TSY-000009
ITU-T G.775,
T1M1.3/93-005
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