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| 型號(hào)： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁(yè)數(shù)： | 11/248頁(yè) |
| 文件大?。?/td> | 1459K |
| 代理商： | T7633 |
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Advance Data Sheet
May 1998
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
Features
The T7633 Dual T1/E1 Terminator consists of two
independent, highly integrated, software-configurable,
full-featured short-haul transceiver/framers. The
T7633 provides glueless interconnection from a T1/
E1 line to a digital PCM system. Minimal external
clocks are needed. Only a system clock/frame sync
and a phase-locked line rate clock are required. Sys-
tem diagnostic and performance monitoring capability
with integrated programmable test pattern generator/
detector and loopback modes is provided.
Power Requirements and Package
I
Single 3.3 V
Low power: 375 mW per channel maximum.
144-pin TQFP package.
Operating temperature range: –40
±
5% supply.
I
I
I
°
C to +85
°
C.
T1/E1 Line Interface Features
I
Full T1/E1 pulse template compliance.
Receiver provides equalization for up to 11 dB of
loss.
Digital clock and data recovery.
Line coding: B8ZS, HDB3, ZCS, and AMI.
Line interface coupling and matching networks for
T1 and E1 (120
and 75
I
I
I
I
).
T1/E1 Framer Features
I
Supports T1 framing modes ESF, D4,
T1DM DDS.
Supports G.704 basic and CRC-4 multiframe for-
mat E1 framing and procedures consistent with
G.706.
Supports unframed transmission format.
T1 signaling modes: transparent; ESF 2-state,
4-state, and 16-state; D4 2-state and 4-state;
96 2-state, 4-state, 9-state, and 16-state. E1 signal-
ing modes: transparent, CAS, CCS, and IRMS.
SLC
-96,
I
I
I
SLC
-
I
Alarm reporting and performance monitoring per
AT&T, ANSI, and ITU-T standards.
Programmable, independent transmit and receive
system interfaces at a 2.048 MHz, 4.096 MHz, or
8.192 MHz data rate.
System interface master mode for generation of
system frame sync from the line source.
Internal phase-locked loop (with external VCXO) for
generation of system clock from the line source.
I
I
I
Facility Data Link Features
I
HDLC or transparent modes.
Automatic transmission and detection of ANSI
T1.403 FDL performance report message and bit-
oriented codes.
64-byte FIFO in both transmit and receive direc-
tions.
I
I
Microprocessor Interface
I
33 MHz, 8-bit data interface, no wait-states.
Intel
* or
Motorola
interface modes with multiplexed
or demultiplexed buses.
Directly addressable control registers.
I
I
Applications
I
Customer Premises Equipment—
routers, digital PBX, channel banks (CB), base
transceiver stations (BTS-picocell), small switches,
and digital subscriber loop access multiplexers
(DSLAM).
Loop/Access
—DLC/IDLC, DCS, BTS (microcell/
macrocell), DSLAMs, and multiplexers (terminal,
synchronous/asynchronous, add drop).
Central Office
—Digital switches, DCS, CB, access
concentrators, remote switch modules (RSM), and
DSLAMs.
Test Equipment
—Transmission/BERT tester.
CSU/DSU,
I
I
I
*
Intel
Motorola
is a registered trademark of Intel Corporation.
is a registered trademark of Motorola, Inc.
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