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參數(shù)資料
| 型號(hào)： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁(yè)數(shù)： | 159/248頁(yè) |
| 文件大小： | 1459K |
| 代理商： | T7633 |
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Advance Data Sheet
May 1998
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
149
Lucent Technologies Inc.
Reset
Both hardware and software resets are provided.
Hardware Reset (Pin 43/139)
Hardware reset is enabled by asserting RESET to 0. Each channel has independent resets, RESET1 (pin 139) for
channel 1 and RESET2 (pin 43) for channel 2. The device is in an inactive condition when RESET is 0, and
becomes active when RESET is returned to 1. Upon completion of a reset cycle, the LIU register default values are
controlled by the setting of DS1/CEPT (pin 40/142), as given in Table 6, Transmit Line Interface Short-Haul Equal-
izer/Rate Control, on page 34. If DS1/CEPT is 1, the defaults are set for DS1 with line equalization for a 1 ft. to
131 ft. span. If DS1/CEPT is 0, the defaults are set for CEPT with a line equalization for 120
twisted pair or
75
coax option 1.
Hardware reset of a single channel returns all LIU, framer, and FDL registers of that channel to their default values,
as listed in the individual register descriptions and register maps, Table 200—Table 206. Reset of a single channel
does not reset the global registers. Hardware reset of both channels simultaneously, both pin 43 and pin 139 set to
0, results in a complete device reset including a reset of the global registers.
Software Reset/Software Restart
Independent software reset for each functional block of the device is available. The LIU may be placed in restart
through register LIU_REG2 bit 5 (RESTART). The framer may be reset through register FRM_PR26 bit 0 (SWRE-
SET), or placed in restart through FRM_PR26 bit 1 (SWRESTART). The FDL receiver may be reset through regis-
ter FDL_PR26 bit 1 (FRR), and the FDL transmitter may be reset through FDL_PR1 bit 5 (FTR). The reset
functions, framer SWRESET (framer software reset), FDL FRR (FDL receiver reset), and FTR (FDL transmitter
reset), reset the block and return all parameter/control registers for the block to their default values. The restart
functions, LIU RESTART and framer SWRESTART (framer software restart), reset the block but do not alter the
value of the parameter/control registers.
Interrupt Generation
An interrupt may be generated by any of the conditions reported in the status registers. For a bit (condition) in a
status register to create an interrupt, the corresponding interrupt enable bit must be set and the interrupt block
enable in the global register for the source block must be set, see Table 70 below. Once the source interrupt regis-
ter is read, the interrupt for that condition is deasserted.
Table 70. Status Register and Corresponding Interrupt Enable Register for Functional Blocks
Default for interrupt assertion is a logical 1 (high) value. But the assertion value and deasserted state is program-
mable through register GREG4 bit 4 and bit 6 and may take on the following state, see Table 71 below.
Table 71. Asserted Value and Deasserted State for GREG4 Bit 4 and Bit 6 Logic Combinations
Functional Block
Status Register
GREG0
LIU_REG0
FRM_SR0—FRM_SR7
FDL_SR0
Interrupt Enable Register
GREG1
LIU_REG1
FRM_PR0—FRM_PR7
FDL_PR2
Primary Block
Line Interface
Framer
Facility Data Link
Greg4
INTERRUPT (Pin 99)
Functionality
Bit 4
0
1
0
1
Bit 6
0
0
1
1
Asserted Value
High
High
Low
Low
Deasserted Value
Low
3-state
High
3-state
—
Wired OR
—
Wired AND
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