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| 型號(hào)： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁(yè)數(shù)： | 226/248頁(yè) |
| 文件大?。?/td> | 1459K |
| 代理商： | T7633 |
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Advance Data Sheet
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
May 1998
216
Lucent Technologies Inc.
FDL Parameter/Control Registers (800—80E; E00—E0E)
(continued)
Table 193. FDL Transparent Control Register (FDL_PR9) (809; E09)
* The octet boundary is relative the first receive clock edge after the receiver has been enabled (ENR, FDL_PR1 bit 2 = 1).
Table 194. FDL Transmit ANSI ESF Bit Codes (FDL_PR10) (80A; E0A)
Bit
0—2
Symbol
FOCTOF0—
FOCTOF2
Description
FDL Octet Offset (Read Only).
These bits record the offset relative to the octet bound-
ary when the receive character was matched. The FOCTOF bits are valid when register
FDL_PR9 bit 3 (FMSTAT) is set to 1. A value of 111 (binary) indicates byte alignment.
Match Status (Read Only).
When this bit is set to 1 by the receive FDL unit, the receiver
match character has been recognized. The octet offset status bits (FDL_PR9 bit[2:0])
indicates the offset relative to the octet boundary* at which the receive character was
matched. If no match is being performed (register FDL_PR9 bit 5 = 0), the FMSTAT bit is
set to 1 automatically when the first byte is received, and the octet offset status bits (reg-
ister FDL_PR9 bit 0—bit 2) are set to 111 (binary).
Frame-Sync Align.
When this bit is set to 1, the receive FDL unit searches for the
receive match character (FDL-PR8) only on an octet boundary. When this bit is 0, the
receive FDL unit searches for the receive match character in a sliding window fashion.
Pattern Match.
FMATCH affects both the transmitter and receiver. When this bit is set to
1, the FDL does not load data into the receive FIFO until the receive match character
programmed in register FDL_PR8 has been detected. The search for the receive match
character is in a sliding window fashion if register FDL_PR9 bit 4 is 0, or only on octet
boundaries if register FDL_PR9 bit 4 is set to 1. When this bit is 0, the receive FDL unit
loads the matched byte and all subsequent data directly into the receive FIFO. On the
transmit side, when this bit is set to 1 the transmitter sends the transmit idle character
programmed into register FDL_PR5 when the transmit FIFO has no user data. The
default idle is to transmit the HDLC 1s idle character (FF hexadecimal); however, any
value can be used by programming the transmit idle character register FDL_PR5. If this
bit is 0, the transmitter sends 1s idle characters when the transmit FIFO is empty.
FDL Transparent Mode.
When this bit is set to 1, the FDL unit performs no HDLC pro-
cessing on incoming or outgoing data.
Reserved.
Write to 0.
3
FMSTAT
4
FALOCT
5
FMATCH
6
FTM
7
—
Bit
0—5
Symbol
FTANSI0—
FTANSI5
—
FTANSI
Description
FDL ESF Bit-Oriented Message Data.
The transmit ESF FDL bit messages are in the
form 111111110X
0
X
1
X
2
X
3
X
4
X
5
0, where the order of transmission is from left to right.
Reserved.
Write to 0.
Transmit ANSI Bit Codes.
When this bit is set to 1, the FDL unit will continuously trans-
mit the ANSI code defined using register FDL_PR10 bit 0—bit 5 as the ESF bit code
messages. This bit must stay high long enough to ensure the ANSI code is sent at least
10 times.
6
7
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